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250 lines
8.7 KiB
250 lines
8.7 KiB
/* |
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* Copyright (C) 2014 The Android Open Source Project |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); |
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* you may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0 |
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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#define ENTRY(f) .text; .align 4; .globl f; .type f,#function; f: |
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#define END(f) .size f, .-f; |
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.macro lanepair dst, src0, src1, xr0, xr1, yr0, yr1, zr0, zr1 |
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smov x6, \src0 |
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smov x7, \src1 |
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add x6, x6, x3 |
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add x7, x7, x3 |
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ld1 {v16.2s}, [x6], x4 |
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ld1 {v17.2s}, [x7], x4 |
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ld1 {v18.2s}, [x6], x5 |
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ld1 {v19.2s}, [x7], x5 |
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dup v8.8b, \yr0 |
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dup v9.8b, \yr1 |
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/* Y interpolate, front, lanes 0 and 1 -> v12 and v13 */ |
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zip1 v12.16b, v5.16b, v16.16b |
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zip1 v13.16b, v5.16b, v17.16b |
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umlsl v12.8h, v16.8b, v8.8b |
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umlsl v13.8h, v17.8b, v9.8b |
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umlal v12.8h, v18.8b, v8.8b |
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umlal v13.8h, v19.8b, v9.8b |
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ld1 {v18.2s}, [x6] |
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ld1 {v19.2s}, [x7] |
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sub x6, x6, x4 |
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sub x7, x7, x4 |
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ld1 {v16.2s}, [x6] |
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ld1 {v17.2s}, [x7] |
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/* Y interpolate, rear, lanes 0 and 1 -> v14 and v15 */ |
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zip1 v14.16b, v5.16b, v16.16b |
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zip1 v15.16b, v5.16b, v17.16b |
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umlsl v14.8h, v16.8b, v8.8b |
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umlsl v15.8h, v17.8b, v9.8b |
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umlal v14.8h, v18.8b, v8.8b |
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umlal v15.8h, v19.8b, v9.8b |
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/* Z interpolate, lane 0 v12/v14 -> v10 */ |
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ushll v8.4s, v12.4h, #8 |
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ushll2 v9.4s, v12.8h, #8 |
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umlsl v8.4s, v12.4h, \zr0 |
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umlsl2 v9.4s, v12.8h, \zr0 |
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umlal v8.4s, v14.4h, \zr0 |
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umlal2 v9.4s, v14.8h, \zr0 |
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rshrn v10.4h, v8.4s, #8 |
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rshrn2 v10.8h, v9.4s, #8 |
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/* Z interpolate, lane 1 v13/v15 -> v11 */ |
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ushll v8.4s, v13.4h, #8 |
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ushll2 v9.4s, v13.8h, #8 |
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umlsl v8.4s, v13.4h, \zr1 |
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umlsl2 v9.4s, v13.8h, \zr1 |
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umlal v8.4s, v15.4h, \zr1 |
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umlal2 v9.4s, v15.8h, \zr1 |
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rshrn v11.4h, v8.4s, #8 |
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rshrn2 v11.8h, v9.4s, #8 |
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/* X interpolate, lanes 0 and 1 v10,v11 -> v14 */ |
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ushll v8.4s, v10.4h, #8 |
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ushll v9.4s, v11.4h, #8 |
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umlsl v8.4s, v10.4h, \xr0 |
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umlsl v9.4s, v11.4h, \xr1 |
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umlal2 v8.4s, v10.8h, \xr0 |
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umlal2 v9.4s, v11.8h, \xr1 |
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shrn v14.4h, v8.4s, #8 |
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shrn2 v14.8h, v9.4s, #8 |
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/* pack lanes 0-1 -> v6 */ |
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.ifc \dst, v20.16b |
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uqrshrn2 \dst, v14.8h, #8 |
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.else ; .ifc \dst, v21.16b |
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uqrshrn2 \dst, v14.8h, #8 |
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.else |
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uqrshrn \dst, v14.8h, #8 |
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.endif ; .endif |
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.endm |
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/* void rsdIntrinsic3DLUT_K( |
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* void *dst, // x0 |
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* void const *in, // x1 |
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* size_t count, // x2 |
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* void const *lut, // x3 |
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* int32_t pitchy, // w4 |
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* int32_t pitchz, // w5 |
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* int dimx, // w6 |
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* int dimy, // w7 |
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* int dimz); // [sp] |
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*/ |
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ENTRY(rsdIntrinsic3DLUT_K) |
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ldr w8, [sp] |
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stp d8, d9, [sp, #-64]! |
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stp d10, d11, [sp, #16] |
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stp d12, d13, [sp, #32] |
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stp d14, d15, [sp, #48] |
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movi v4.8b, #1 |
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ins v4.h[0], w6 |
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ins v4.h[1], w7 |
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ins v4.h[2], w8 |
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ins v4.s[2], w4 |
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ins v4.s[3], w5 |
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movi v5.16b, #0 |
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subs x2, x2, #8 |
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bge 2f |
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cmn x2, #8 // same as cmp x2, #-8 |
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ble 9f |
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b 4f |
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.align 6 |
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1: st4 {v20.8b,v21.8b,v22.8b,v23.8b}, [x0], #32 |
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/* x0 = dst |
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* x1 = src |
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* x2 = count |
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* x3 = lut |
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* x4 = pitchy |
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* x5 = pitchz |
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* x6 = offset0 |
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* x7 = offset1 |
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*/ |
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2: ld4 {v0.8b-v3.8b}, [x1], #32 |
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/* v0,v1,v2,v3 source data |
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* v4 dimensions and pitches |
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*/ |
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3: uxtl v0.8h, v0.8b |
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uxtl v1.8h, v1.8b |
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uxtl v2.8h, v2.8b |
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mul v0.8h, v0.8h, v4.h[0] |
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mul v1.8h, v1.8h, v4.h[1] |
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mul v2.8h, v2.8h, v4.h[2] |
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/* ursra below would be more accurate, but this can result in a dim.0 case |
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* where we try to read from the limit of the array and the limit +1 to |
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* interpolate, even though the fractional component is zero. Strictly this is |
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* correct, except for the llegal access problem. |
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*/ |
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usra v0.8h, v0.8h, #8 |
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usra v1.8h, v1.8h, #8 |
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usra v2.8h, v2.8h, #8 |
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ushr v12.8h, v0.8h, #8 |
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ushr v13.8h, v1.8h, #8 |
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ushr v14.8h, v2.8h, #8 |
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bic v0.8h, #0xff, LSL #8 |
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xtn v1.8b, v1.8h |
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bic v2.8h, #0xff, LSL #8 |
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/* v0.8h,v1.8b,v2.hb fractional offset |
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* v12.8h,v13.8h,v14.8h integer offset |
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*/ |
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ushll v6.4s, v12.4h, #2 |
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ushll2 v7.4s, v12.8h, #2 |
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uxtl v8.4s, v13.4h |
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uxtl2 v9.4s, v13.8h |
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uxtl v10.4s, v14.4h |
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uxtl2 v11.4s, v14.8h |
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mla v6.4s, v8.4s, v4.s[2] |
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mla v7.4s, v9.4s, v4.s[2] |
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mla v6.4s, v10.4s, v4.s[3] |
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mla v7.4s, v11.4s, v4.s[3] |
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/* v6,v7 list of table offsets */ |
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/* lanes 0 and 1 */ |
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lanepair dst=v20.8b, src0=v6.s[0], src1=v6.s[1], xr0=v0.h[0], xr1=v0.h[1], yr0=v1.b[0], yr1=v1.b[1], zr0=v2.h[0], zr1=v2.h[1] |
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/* lanes 2 and 3 */ |
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lanepair dst=v20.16b, src0=v6.s[2], src1=v6.s[3], xr0=v0.h[2], xr1=v0.h[3], yr0=v1.b[2], yr1=v1.b[3], zr0=v2.h[2], zr1=v2.h[3] |
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/* lanes 4 and 5 */ |
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lanepair dst=v21.8b, src0=v7.s[0], src1=v7.s[1], xr0=v0.h[4], xr1=v0.h[5], yr0=v1.b[4], yr1=v1.b[5], zr0=v2.h[4], zr1=v2.h[5] |
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/* lanes 6 and 7 */ |
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lanepair dst=v21.16b, src0=v7.s[2], src1=v7.s[3], xr0=v0.h[6], xr1=v0.h[7], yr0=v1.b[6], yr1=v1.b[7], zr0=v2.h[6], zr1=v2.h[7] |
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uzp1 v6.16b, v20.16b, v21.16b |
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uzp2 v7.16b, v20.16b, v21.16b |
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uzp1 v20.16b, v6.16b, v7.16b |
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uzp2 v22.16b, v6.16b, v7.16b |
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mov v21.d[0], v20.d[1] |
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subs x2, x2, #8 |
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mov v23.8b, v3.8b |
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bge 1b |
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cmn x2, #8 // same as cmp x2, #-8 |
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blt 1f |
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st4 {v20.8b,v21.8b,v22.8b,v23.8b}, [x0], #32 |
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beq 9f |
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/* fill the vector with a safe value */ |
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4: ld4r {v0.8b-v3.8b}, [x1] |
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tbz x2, #2, 2f |
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ld4 {v0.b-v3.b}[0], [x1], #4 |
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ld4 {v0.b-v3.b}[1], [x1], #4 |
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ld4 {v0.b-v3.b}[2], [x1], #4 |
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ld4 {v0.b-v3.b}[3], [x1], #4 |
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2: tbz x2, #1, 2f |
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ld4 {v0.b-v3.b}[4], [x1], #4 |
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ld4 {v0.b-v3.b}[5], [x1], #4 |
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2: tbz x2, #0, 2f |
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ld4 {v0.b-v3.b}[6], [x1], #4 |
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2: b 3b |
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1: tst x2, #4 |
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beq 2f |
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st4 {v20.b-v23.b}[0], [x0], #4 |
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st4 {v20.b-v23.b}[1], [x0], #4 |
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st4 {v20.b-v23.b}[2], [x0], #4 |
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st4 {v20.b-v23.b}[3], [x0], #4 |
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2: tst x2, #2 |
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beq 2f |
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st4 {v20.b-v23.b}[4], [x0], #4 |
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st4 {v20.b-v23.b}[5], [x0], #4 |
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2: tst x2, #1 |
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beq 9f |
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st4 {v20.b-v23.b}[6], [x0], #4 |
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9: ldp d14, d15, [sp, #48] |
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ldp d12, d13, [sp, #32] |
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ldp d10, d11, [sp, #16] |
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ldp d8, d9, [sp], #64 |
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ret |
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END(rsdIntrinsic3DLUT_K)
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