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479 lines
12 KiB
479 lines
12 KiB
/* |
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* Copyright (C) 2018 MediaTek Inc. |
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|
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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|
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details. |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/mfd/core.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/of_irq.h> |
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#include <linux/regmap.h> |
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#if defined(CONFIG_MTK_PMIC_CHIP_MT6357) |
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#include <linux/mfd/mt6357/irq.h> |
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#include <linux/mfd/mt6357/registers.h> |
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#elif defined(CONFIG_MTK_PMIC_CHIP_MT6358) |
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#include <linux/mfd/mt6358/irq.h> |
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#include <linux/mfd/mt6358/registers.h> |
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#elif defined(CONFIG_MTK_PMIC_CHIP_MT6359) |
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#include <linux/mfd/mt6359/irq.h> |
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#include <linux/mfd/mt6359/registers.h> |
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#elif defined(CONFIG_MTK_PMIC_CHIP_MT6359P) |
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#include <linux/mfd/mt6359p/irq.h> |
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#include <linux/mfd/mt6359p/registers.h> |
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#endif |
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#include <linux/mfd/mt6358/core.h> |
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#define MT6357_CID_CODE 0x5700 |
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#define MT6358_CID_CODE 0x5800 |
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#define MT6359_CID_CODE 0x5900 |
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static const struct mfd_cell mt6357_devs[] = { |
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{ |
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.name = "mt-pmic", |
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.of_compatible = "mediatek,mt-pmic", |
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}, { |
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.name = "mt635x-auxadc", |
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.of_compatible = "mediatek,mt6357-auxadc", |
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}, |
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}; |
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static const struct mfd_cell mt6358_devs[] = { |
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{ |
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.name = "mt-pmic", |
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.of_compatible = "mediatek,mt-pmic", |
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}, { |
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.name = "mt635x-auxadc", |
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.of_compatible = "mediatek,mt6358-auxadc", |
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}, { |
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.name = "mt6358-regulator", |
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.of_compatible = "mediatek,mt6358-regulator", |
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}, { |
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.name = "mt6358-rtc", |
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.of_compatible = "mediatek,mt6358-rtc", |
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}, { |
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.name = "mt6358-misc", |
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.of_compatible = "mediatek,mt6358-misc", |
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}, |
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}; |
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static const struct mfd_cell mt6359_devs[] = { |
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{ |
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.name = "mt-pmic", |
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.of_compatible = "mediatek,mt-pmic", |
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}, { |
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.name = "mt635x-auxadc", |
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.of_compatible = "mediatek,mt6359-auxadc", |
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}, { |
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.name = "mt6359-regulator", |
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.of_compatible = "mediatek,mt6359-regulator", |
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}, { |
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.name = "mt6359p-regulator", |
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.of_compatible = "mediatek,mt6359p-regulator", |
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}, { |
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.name = "mt6359-rtc", |
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.of_compatible = "mediatek,mt6359-rtc", |
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}, { |
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.name = "mt6359-misc", |
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.of_compatible = "mediatek,mt6359-misc", |
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}, |
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{ |
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.name = "mt6359p-misc", |
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.of_compatible = "mediatek,mt6359p-misc", |
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}, |
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}; |
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struct sp_top_t { |
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int hwirq_base; |
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unsigned int num_int_regs; |
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unsigned int en_reg; |
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unsigned int mask_reg; |
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unsigned int sta_reg; |
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unsigned int raw_sta_reg; |
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unsigned int top_offset; |
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}; |
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struct pmic_irq_t { |
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const char *name; |
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int hwirq; |
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struct sp_top_t *sp_top; |
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}; |
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static struct sp_top_t sp_top_ints[] = { |
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SP_TOP_GEN(BUCK), |
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SP_TOP_GEN(LDO), |
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SP_TOP_GEN(PSC), |
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SP_TOP_GEN(SCK), |
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SP_TOP_GEN(BM), |
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SP_TOP_GEN(HK), |
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SP_TOP_GEN(AUD), |
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SP_TOP_GEN(MISC), |
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}; |
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static struct pmic_irq_t *pmic_irqs; |
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unsigned int mt6358_irq_get_virq(struct device *dev, unsigned int hwirq) |
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{ |
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struct mt6358_chip *chip = dev_get_drvdata(dev); |
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return irq_create_mapping(chip->irq_domain, hwirq); |
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} |
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EXPORT_SYMBOL(mt6358_irq_get_virq); |
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const char *mt6358_irq_get_name(struct device *dev, unsigned int hwirq) |
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{ |
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struct mt6358_chip *chip = dev_get_drvdata(dev); |
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if (hwirq >= chip->num_pmic_irqs) |
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return NULL; |
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return pmic_irqs[hwirq].name; |
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} |
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EXPORT_SYMBOL(mt6358_irq_get_name); |
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static void mt6358_irq_sp_handler(struct mt6358_chip *chip, |
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unsigned int sp) |
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{ |
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unsigned int sta_reg, sp_int_status = 0; |
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unsigned int hwirq, virq; |
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int ret, i, j; |
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for (i = 0; i < sp_top_ints[sp].num_int_regs; i++) { |
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sta_reg = sp_top_ints[sp].sta_reg + 0x2 * i; |
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ret = regmap_read(chip->regmap, sta_reg, &sp_int_status); |
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if (ret) { |
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dev_notice(chip->dev, |
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"Failed to read irq status: %d\n", ret); |
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return; |
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} |
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if (!sp_int_status) |
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continue; |
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for (j = 0; j < 16 ; j++) { |
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if ((sp_int_status & BIT(j)) == 0) |
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continue; |
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hwirq = sp_top_ints[sp].hwirq_base + 16 * i + j; |
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virq = irq_find_mapping(chip->irq_domain, hwirq); |
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dev_info(chip->dev, |
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"Reg[0x%x]=0x%x,name=%s,hwirq=%d,type=%d\n", |
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sta_reg, sp_int_status, |
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pmic_irqs[hwirq].name, hwirq, |
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irq_get_trigger_type(virq)); |
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if (virq) |
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handle_nested_irq(virq); |
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} |
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regmap_write(chip->regmap, sta_reg, sp_int_status); |
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} |
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} |
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static irqreturn_t mt6358_irq_handler(int irq, void *data) |
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{ |
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struct mt6358_chip *chip = data; |
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unsigned int top_int_status = 0; |
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unsigned int i; |
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int ret; |
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pm_stay_awake(chip->dev); |
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ret = regmap_read(chip->regmap, |
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chip->top_int_status_reg, |
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&top_int_status); |
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if (ret) { |
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dev_notice(chip->dev, "Can't read TOP_INT_STATUS ret=%d\n", |
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ret); |
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return IRQ_NONE; |
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} |
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for (i = 0; i < chip->num_sps; i++) { |
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if (top_int_status & BIT(sp_top_ints[i].top_offset)) |
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mt6358_irq_sp_handler(chip, i); |
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} |
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pm_relax(chip->dev); |
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return IRQ_HANDLED; |
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} |
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static void mt6358_irq_enable(struct irq_data *data) |
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{ |
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unsigned int en_reg, int_regs; |
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unsigned int hwirq = irqd_to_hwirq(data); |
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struct sp_top_t *sp_top = pmic_irqs[hwirq].sp_top; |
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struct mt6358_chip *chip = irq_data_get_irq_chip_data(data); |
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int_regs = (hwirq - sp_top->hwirq_base) / 16; |
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en_reg = sp_top->en_reg + 0x6 * int_regs; |
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regmap_write(chip->regmap, en_reg + 0x2, 0x1 << (hwirq % 16)); |
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} |
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static void mt6358_irq_disable(struct irq_data *data) |
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{ |
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unsigned int en_reg, int_regs; |
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unsigned int hwirq = irqd_to_hwirq(data); |
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struct sp_top_t *sp_top = pmic_irqs[hwirq].sp_top; |
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struct mt6358_chip *chip = irq_data_get_irq_chip_data(data); |
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int_regs = (hwirq - sp_top->hwirq_base) / 16; |
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en_reg = sp_top->en_reg + 0x6 * int_regs; |
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regmap_write(chip->regmap, en_reg + 0x4, 0x1 << (hwirq % 16)); |
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} |
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static void mt6358_irq_lock(struct irq_data *data) |
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{ |
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struct mt6358_chip *chip = irq_data_get_irq_chip_data(data); |
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mutex_lock(&chip->irqlock); |
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} |
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static void mt6358_irq_sync_unlock(struct irq_data *data) |
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{ |
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struct mt6358_chip *chip = irq_data_get_irq_chip_data(data); |
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mutex_unlock(&chip->irqlock); |
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} |
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static int mt6358_irq_set_type(struct irq_data *data, unsigned int type) |
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{ |
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return 0; |
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} |
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static struct irq_chip mt6358_irq_chip = { |
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.name = "mt6358-irq", |
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.irq_enable = mt6358_irq_enable, |
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.irq_disable = mt6358_irq_disable, |
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.irq_bus_lock = mt6358_irq_lock, |
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.irq_bus_sync_unlock = mt6358_irq_sync_unlock, |
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.irq_set_type = mt6358_irq_set_type, |
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}; |
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static int mt6358_irq_domain_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hwirq) |
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{ |
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struct mt6358_chip *chip = d->host_data; |
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irq_set_chip_data(irq, chip); |
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irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq); |
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irq_set_nested_thread(irq, 1); |
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irq_set_noprobe(irq); |
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return 0; |
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} |
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static const struct irq_domain_ops mt6358_irq_domain_ops = { |
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.map = mt6358_irq_domain_map, |
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.xlate = irq_domain_xlate_twocell, |
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}; |
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static int mt6358_irq_init(struct mt6358_chip *chip) |
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{ |
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int i, ret = 0; |
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if (chip->irq <= 0) { |
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dev_notice(chip->dev, |
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"failed to get platform irq, ret=%d", chip->irq); |
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return 0; |
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} |
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mutex_init(&chip->irqlock); |
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ret = of_property_read_u32(chip->dev->of_node, |
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"mediatek,num-pmic-irqs", |
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&chip->num_pmic_irqs); |
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if (ret) { |
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dev_notice(chip->dev, "no number of pmic_irqs\n"); |
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return -EINVAL; |
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} |
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chip->num_sps = ARRAY_SIZE(sp_top_ints); |
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pmic_irqs = devm_kcalloc(chip->dev, chip->num_pmic_irqs, |
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sizeof(struct pmic_irq_t), GFP_KERNEL); |
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for (i = 0; i < chip->num_pmic_irqs; i++) { |
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const char *name = NULL; |
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unsigned int hwirq = 0, sp = 0, num_int_bits; |
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struct pmic_irq_t *pmic_irq; |
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ret = of_property_read_string_index(chip->dev->of_node, |
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"interrupt-names", |
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i, &name); |
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if (ret < 0) |
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break; |
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ret = of_property_read_u32_index(chip->dev->of_node, |
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"mediatek,pmic-irqs", |
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i * 2 + 0, &hwirq); |
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ret |= of_property_read_u32_index(chip->dev->of_node, |
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"mediatek,pmic-irqs", |
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i * 2 + 1, &sp); |
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if (ret < 0) { |
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dev_notice(chip->dev, "%s missing pmic-irqs\n", name); |
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break; |
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} else if (sp >= chip->num_sps) { |
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dev_notice(chip->dev, "%s has invalid sp %d\n", |
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name, sp); |
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break; |
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} |
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pmic_irq = pmic_irqs + hwirq; |
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pmic_irq->name = name; |
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pmic_irq->hwirq = hwirq; |
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pmic_irq->sp_top = &sp_top_ints[sp]; |
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num_int_bits = sp_top_ints[sp].num_int_regs * 16; |
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if (pmic_irq->sp_top->hwirq_base == -1) |
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pmic_irq->sp_top->hwirq_base = round_down(hwirq, 16); |
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else if (hwirq - pmic_irq->sp_top->hwirq_base >= num_int_bits) |
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pmic_irq->sp_top->num_int_regs++; |
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#if 0 |
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dev_info(chip->dev, |
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"name:%s, hwirq:%d, sp_top:%d, hwirq_base:%d, num_int_regs:%d, ret:%d\n" |
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, pmic_irq->name, pmic_irq->hwirq, |
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sp, pmic_irq->sp_top->hwirq_base, |
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pmic_irq->sp_top->num_int_regs, ret); |
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#endif |
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} |
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/* Disable all interrupt for initializing */ |
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for (i = 0; i < chip->num_sps; i++) { |
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int j; |
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for (j = 0; j < sp_top_ints[i].num_int_regs; j++) |
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regmap_write(chip->regmap, |
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sp_top_ints[i].en_reg + 0x6 * j, 0); |
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} |
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chip->irq_domain = irq_domain_add_linear(chip->dev->of_node, |
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chip->num_pmic_irqs, |
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&mt6358_irq_domain_ops, |
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chip); |
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if (!chip->irq_domain) { |
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dev_notice(chip->dev, "could not create irq domain\n"); |
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return -ENODEV; |
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} |
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ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL, |
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mt6358_irq_handler, IRQF_ONESHOT, mt6358_irq_chip.name, chip); |
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if (ret) { |
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dev_notice(chip->dev, "failed to register irq=%d; err: %d\n", |
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chip->irq, ret); |
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return 0; |
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} |
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enable_irq_wake(chip->irq); |
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return ret; |
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} |
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static struct mt6358_chip *mt6358_pm_off; |
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static void mt6358_power_off(void) |
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{ |
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pr_info("%s\n", __func__); |
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if (mt6358_pm_off) |
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regmap_update_bits(mt6358_pm_off->regmap, |
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PMIC_RG_PWRHOLD_ADDR, |
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PMIC_RG_PWRHOLD_MASK << PMIC_RG_PWRHOLD_SHIFT, |
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0 << PMIC_RG_PWRHOLD_SHIFT); |
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} |
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static int mt6358_probe(struct platform_device *pdev) |
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{ |
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int ret; |
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unsigned int id = 0; |
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struct mt6358_chip *chip; |
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
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if (!chip) |
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return -ENOMEM; |
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chip->dev = &pdev->dev; |
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chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
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if (!chip->regmap) |
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return -ENODEV; |
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chip->irq = platform_get_irq(pdev, 0); |
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if (chip->irq <= 0) { |
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dev_notice(&pdev->dev, |
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"failed to get platform irq, ret=%d", chip->irq); |
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} |
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platform_set_drvdata(pdev, chip); |
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ret = regmap_read(chip->regmap, PMIC_HWCID_ADDR, &id); |
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if (ret) { |
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dev_notice(chip->dev, "Failed to read chip id: %d\n", ret); |
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return ret; |
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} |
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dev_info(chip->dev, "PMIC irq=%d, PMIC HWCID=0x%x, ret=%d\n", |
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chip->irq, id, ret); |
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mt6358_pm_off = chip; |
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pm_power_off = mt6358_power_off; |
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switch (id & 0xFF00) { |
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case MT6357_CID_CODE: |
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chip->top_int_status_reg = PMIC_INT_STATUS_TOP_RSV_ADDR; |
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ret = mt6358_irq_init(chip); |
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if (ret) |
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return ret; |
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ret = devm_mfd_add_devices(&pdev->dev, -1, mt6357_devs, |
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ARRAY_SIZE(mt6357_devs), NULL, |
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0, chip->irq_domain); |
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break; |
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case MT6358_CID_CODE: |
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chip->top_int_status_reg = PMIC_INT_STATUS_TOP_RSV_ADDR; |
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ret = mt6358_irq_init(chip); |
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if (ret) |
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return ret; |
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ret = devm_mfd_add_devices(&pdev->dev, -1, mt6358_devs, |
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ARRAY_SIZE(mt6358_devs), NULL, |
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0, chip->irq_domain); |
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break; |
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case MT6359_CID_CODE: |
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chip->top_int_status_reg = PMIC_INT_STATUS_TOP_RSV_ADDR; |
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ret = mt6358_irq_init(chip); |
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if (ret) |
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return ret; |
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ret = devm_mfd_add_devices(&pdev->dev, -1, mt6359_devs, |
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ARRAY_SIZE(mt6359_devs), NULL, |
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0, NULL); |
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break; |
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default: |
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dev_notice(&pdev->dev, "unsupported chip: %d\n", id); |
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ret = -ENODEV; |
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break; |
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} |
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if (ret) { |
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irq_domain_remove(chip->irq_domain); |
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dev_notice(&pdev->dev, "failed to add child devices: %d\n", |
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ret); |
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} |
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return ret; |
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} |
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static const struct of_device_id mt6358_of_match[] = { |
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{ |
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.compatible = "mediatek,mt6357-pmic", |
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}, { |
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.compatible = "mediatek,mt6358-pmic", |
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}, { |
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.compatible = "mediatek,mt6359-pmic", |
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}, { |
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/* sentinel */ |
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} |
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}; |
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MODULE_DEVICE_TABLE(of, mt6358_of_match); |
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static struct platform_driver mt6358_driver = { |
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.probe = mt6358_probe, |
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.driver = { |
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.name = "mt6358-pmic", |
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.of_match_table = of_match_ptr(mt6358_of_match), |
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}, |
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}; |
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static int __init mt6358_init(void) |
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{ |
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pr_info("%s!!\n", __func__); |
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return platform_driver_register(&mt6358_driver); |
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} |
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fs_initcall(mt6358_init); |
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MODULE_AUTHOR("Jeter Chen <Jeter.Chen@mediatek.com>"); |
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MODULE_DESCRIPTION("Driver for MediaTek MT6358 PMIC"); |
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MODULE_LICENSE("GPL v2");
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