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317 lines
11 KiB
317 lines
11 KiB
/* |
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* Copyright (c) 2015, Linaro Limited |
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* |
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* This software is licensed under the terms of the GNU General Public |
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* License version 2, as published by the Free Software Foundation, and |
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* may be copied, distributed, and modified under those terms. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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*/ |
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#ifndef __LINUX_ARM_SMCCC_H |
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#define __LINUX_ARM_SMCCC_H |
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#include <uapi/linux/const.h> |
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/* |
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* This file provides common defines for ARM SMC Calling Convention as |
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* specified in |
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* http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html |
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*/ |
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#define ARM_SMCCC_STD_CALL _AC(0,U) |
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#define ARM_SMCCC_FAST_CALL _AC(1,U) |
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#define ARM_SMCCC_TYPE_SHIFT 31 |
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#define ARM_SMCCC_SMC_32 0 |
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#define ARM_SMCCC_SMC_64 1 |
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#define ARM_SMCCC_CALL_CONV_SHIFT 30 |
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#define ARM_SMCCC_OWNER_MASK 0x3F |
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#define ARM_SMCCC_OWNER_SHIFT 24 |
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#define ARM_SMCCC_FUNC_MASK 0xFFFF |
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#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ |
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((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) |
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#define ARM_SMCCC_IS_64(smc_val) \ |
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((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) |
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#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) |
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#define ARM_SMCCC_OWNER_NUM(smc_val) \ |
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(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) |
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#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ |
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(((type) << ARM_SMCCC_TYPE_SHIFT) | \ |
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((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ |
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(((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ |
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((func_num) & ARM_SMCCC_FUNC_MASK)) |
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#define ARM_SMCCC_OWNER_ARCH 0 |
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#define ARM_SMCCC_OWNER_CPU 1 |
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#define ARM_SMCCC_OWNER_SIP 2 |
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#define ARM_SMCCC_OWNER_OEM 3 |
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#define ARM_SMCCC_OWNER_STANDARD 4 |
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#define ARM_SMCCC_OWNER_TRUSTED_APP 48 |
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#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 |
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#define ARM_SMCCC_OWNER_TRUSTED_OS 50 |
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#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 |
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#define ARM_SMCCC_QUIRK_NONE 0 |
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#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ |
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#define ARM_SMCCC_VERSION_1_0 0x10000 |
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#define ARM_SMCCC_VERSION_1_1 0x10001 |
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#define ARM_SMCCC_VERSION_FUNC_ID \ |
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ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ |
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ARM_SMCCC_SMC_32, \ |
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0, 0) |
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#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ |
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ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ |
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ARM_SMCCC_SMC_32, \ |
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0, 1) |
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#define ARM_SMCCC_ARCH_WORKAROUND_1 \ |
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ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ |
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ARM_SMCCC_SMC_32, \ |
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0, 0x8000) |
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#define ARM_SMCCC_ARCH_WORKAROUND_2 \ |
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ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ |
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ARM_SMCCC_SMC_32, \ |
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0, 0x7fff) |
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#ifndef __ASSEMBLY__ |
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#include <linux/linkage.h> |
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#include <linux/types.h> |
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/** |
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* struct arm_smccc_res - Result from SMC/HVC call |
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* @a0-a3 result values from registers 0 to 3 |
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*/ |
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struct arm_smccc_res { |
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unsigned long a0; |
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unsigned long a1; |
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unsigned long a2; |
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unsigned long a3; |
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}; |
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/** |
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* struct arm_smccc_quirk - Contains quirk information |
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* @id: quirk identification |
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* @state: quirk specific information |
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* @a6: Qualcomm quirk entry for returning post-smc call contents of a6 |
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*/ |
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struct arm_smccc_quirk { |
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int id; |
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union { |
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unsigned long a6; |
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} state; |
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}; |
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/** |
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* __arm_smccc_smc() - make SMC calls |
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* @a0-a7: arguments passed in registers 0 to 7 |
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* @res: result values from registers 0 to 3 |
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* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. |
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* |
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* This function is used to make SMC calls following SMC Calling Convention. |
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* The content of the supplied param are copied to registers 0 to 7 prior |
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* to the SMC instruction. The return values are updated with the content |
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* from register 0 to 3 on return from the SMC instruction. An optional |
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* quirk structure provides vendor specific behavior. |
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*/ |
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asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1, |
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unsigned long a2, unsigned long a3, unsigned long a4, |
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unsigned long a5, unsigned long a6, unsigned long a7, |
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struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); |
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/** |
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* __arm_smccc_hvc() - make HVC calls |
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* @a0-a7: arguments passed in registers 0 to 7 |
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* @res: result values from registers 0 to 3 |
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* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. |
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* |
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* This function is used to make HVC calls following SMC Calling |
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* Convention. The content of the supplied param are copied to registers 0 |
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* to 7 prior to the HVC instruction. The return values are updated with |
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* the content from register 0 to 3 on return from the HVC instruction. An |
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* optional quirk structure provides vendor specific behavior. |
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*/ |
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asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, |
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unsigned long a2, unsigned long a3, unsigned long a4, |
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unsigned long a5, unsigned long a6, unsigned long a7, |
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struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); |
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#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) |
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#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) |
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#define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL) |
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#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__) |
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/* SMCCC v1.1 implementation madness follows */ |
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#ifdef CONFIG_ARM64 |
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#define SMCCC_SMC_INST "smc #0" |
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#define SMCCC_HVC_INST "hvc #0" |
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#define SMCCC_REG(n) asm("x" # n) |
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#elif defined(CONFIG_ARM) |
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#include <asm/opcodes-sec.h> |
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#include <asm/opcodes-virt.h> |
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#define SMCCC_SMC_INST __SMC(0) |
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#define SMCCC_HVC_INST __HVC(0) |
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#define SMCCC_REG(n) asm("r" # n) |
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#endif |
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#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x |
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#define __count_args(...) \ |
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___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) |
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#define __constraint_write_0 \ |
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"+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) |
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#define __constraint_write_1 \ |
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"+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) |
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#define __constraint_write_2 \ |
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"+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) |
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#define __constraint_write_3 \ |
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"+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) |
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#define __constraint_write_4 __constraint_write_3 |
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#define __constraint_write_5 __constraint_write_4 |
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#define __constraint_write_6 __constraint_write_5 |
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#define __constraint_write_7 __constraint_write_6 |
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#define __constraint_read_0 |
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#define __constraint_read_1 |
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#define __constraint_read_2 |
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#define __constraint_read_3 |
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#define __constraint_read_4 "r" (r4) |
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#define __constraint_read_5 __constraint_read_4, "r" (r5) |
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#define __constraint_read_6 __constraint_read_5, "r" (r6) |
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#define __constraint_read_7 __constraint_read_6, "r" (r7) |
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#define __declare_arg_0(a0, res) \ |
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struct arm_smccc_res *___res = res; \ |
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register unsigned long r0 SMCCC_REG(0) = (u32)a0; \ |
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register unsigned long r1 SMCCC_REG(1); \ |
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register unsigned long r2 SMCCC_REG(2); \ |
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register unsigned long r3 SMCCC_REG(3) |
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#define __declare_arg_1(a0, a1, res) \ |
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typeof(a1) __a1 = a1; \ |
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struct arm_smccc_res *___res = res; \ |
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register unsigned long r0 SMCCC_REG(0) = (u32)a0; \ |
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register unsigned long r1 SMCCC_REG(1) = __a1; \ |
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register unsigned long r2 SMCCC_REG(2); \ |
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register unsigned long r3 SMCCC_REG(3) |
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#define __declare_arg_2(a0, a1, a2, res) \ |
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typeof(a1) __a1 = a1; \ |
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typeof(a2) __a2 = a2; \ |
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struct arm_smccc_res *___res = res; \ |
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register unsigned long r0 SMCCC_REG(0) = (u32)a0; \ |
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register unsigned long r1 SMCCC_REG(1) = __a1; \ |
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register unsigned long r2 SMCCC_REG(2) = __a2; \ |
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register unsigned long r3 SMCCC_REG(3) |
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#define __declare_arg_3(a0, a1, a2, a3, res) \ |
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typeof(a1) __a1 = a1; \ |
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typeof(a2) __a2 = a2; \ |
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typeof(a3) __a3 = a3; \ |
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struct arm_smccc_res *___res = res; \ |
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register unsigned long r0 SMCCC_REG(0) = (u32)a0; \ |
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register unsigned long r1 SMCCC_REG(1) = __a1; \ |
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register unsigned long r2 SMCCC_REG(2) = __a2; \ |
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register unsigned long r3 SMCCC_REG(3) = __a3 |
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#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ |
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typeof(a4) __a4 = a4; \ |
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__declare_arg_3(a0, a1, a2, a3, res); \ |
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register unsigned long r4 SMCCC_REG(4) = __a4 |
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#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ |
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typeof(a5) __a5 = a5; \ |
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__declare_arg_4(a0, a1, a2, a3, a4, res); \ |
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register unsigned long r5 SMCCC_REG(5) = __a5 |
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#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ |
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typeof(a6) __a6 = a6; \ |
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__declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ |
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register unsigned long r6 SMCCC_REG(6) = __a6 |
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#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ |
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typeof(a7) __a7 = a7; \ |
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__declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ |
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register unsigned long r7 SMCCC_REG(7) = __a7 |
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#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) |
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#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) |
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#define ___constraints(count) \ |
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: __constraint_write_ ## count \ |
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: __constraint_read_ ## count \ |
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: "memory" |
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#define __constraints(count) ___constraints(count) |
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/* |
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* We have an output list that is not necessarily used, and GCC feels |
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* entitled to optimise the whole sequence away. "volatile" is what |
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* makes it stick. |
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*/ |
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#define __arm_smccc_1_1(inst, ...) \ |
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do { \ |
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__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ |
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asm volatile(inst "\n" \ |
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__constraints(__count_args(__VA_ARGS__))); \ |
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if (___res) \ |
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*___res = (typeof(*___res)){r0, r1, r2, r3}; \ |
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} while (0) |
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/* |
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* arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call |
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* |
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* This is a variadic macro taking one to eight source arguments, and |
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* an optional return structure. |
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* |
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* @a0-a7: arguments passed in registers 0 to 7 |
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* @res: result values from registers 0 to 3 |
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* |
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* This macro is used to make SMC calls following SMC Calling Convention v1.1. |
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* The content of the supplied param are copied to registers 0 to 7 prior |
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* to the SMC instruction. The return values are updated with the content |
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* from register 0 to 3 on return from the SMC instruction if not NULL. |
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*/ |
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#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) |
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/* |
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* arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call |
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* |
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* This is a variadic macro taking one to eight source arguments, and |
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* an optional return structure. |
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* |
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* @a0-a7: arguments passed in registers 0 to 7 |
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* @res: result values from registers 0 to 3 |
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* |
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* This macro is used to make HVC calls following SMC Calling Convention v1.1. |
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* The content of the supplied param are copied to registers 0 to 7 prior |
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* to the HVC instruction. The return values are updated with the content |
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* from register 0 to 3 on return from the HVC instruction if not NULL. |
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*/ |
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#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) |
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/* Return codes defined in ARM DEN 0070A */ |
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#define SMCCC_RET_SUCCESS 0 |
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#define SMCCC_RET_NOT_SUPPORTED -1 |
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#define SMCCC_RET_NOT_REQUIRED -2 |
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#endif /*__ASSEMBLY__*/ |
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#endif /*__LINUX_ARM_SMCCC_H*/
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