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62 lines
1.8 KiB
62 lines
1.8 KiB
/* |
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* STM32 Low-Power Timer parent driver. |
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* |
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* Copyright (C) STMicroelectronics 2017 |
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* |
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com> |
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* |
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* Inspired by Benjamin Gaignard's stm32-timers driver |
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* |
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* License terms: GNU General Public License (GPL), version 2 |
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*/ |
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#ifndef _LINUX_STM32_LPTIMER_H_ |
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#define _LINUX_STM32_LPTIMER_H_ |
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#include <linux/clk.h> |
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#include <linux/regmap.h> |
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#define STM32_LPTIM_ISR 0x00 /* Interrupt and Status Reg */ |
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#define STM32_LPTIM_ICR 0x04 /* Interrupt Clear Reg */ |
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#define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ |
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#define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ |
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#define STM32_LPTIM_CR 0x10 /* Control Reg */ |
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#define STM32_LPTIM_CMP 0x14 /* Compare Reg */ |
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#define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ |
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#define STM32_LPTIM_CNT 0x1C /* Counter Reg */ |
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/* STM32_LPTIM_ISR - bit fields */ |
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#define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) |
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#define STM32_LPTIM_ARROK BIT(4) |
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#define STM32_LPTIM_CMPOK BIT(3) |
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/* STM32_LPTIM_ICR - bit fields */ |
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#define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) |
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/* STM32_LPTIM_CR - bit fields */ |
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#define STM32_LPTIM_CNTSTRT BIT(2) |
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#define STM32_LPTIM_ENABLE BIT(0) |
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/* STM32_LPTIM_CFGR - bit fields */ |
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#define STM32_LPTIM_ENC BIT(24) |
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#define STM32_LPTIM_COUNTMODE BIT(23) |
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#define STM32_LPTIM_WAVPOL BIT(21) |
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#define STM32_LPTIM_PRESC GENMASK(11, 9) |
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#define STM32_LPTIM_CKPOL GENMASK(2, 1) |
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/* STM32_LPTIM_ARR */ |
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#define STM32_LPTIM_MAX_ARR 0xFFFF |
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/** |
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* struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device |
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* @clk: clock reference for this instance |
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* @regmap: register map reference for this instance |
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* @has_encoder: indicates this Low-Power Timer supports encoder mode |
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*/ |
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struct stm32_lptimer { |
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struct clk *clk; |
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struct regmap *regmap; |
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bool has_encoder; |
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}; |
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#endif
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