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327 lines
9.4 KiB
327 lines
9.4 KiB
/* |
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* Copyright (C) 2010 Google, Inc. |
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* |
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* This software is licensed under the terms of the GNU General Public |
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* License version 2, as published by the Free Software Foundation, and |
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* may be copied, distributed, and modified under those terms. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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*/ |
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#include <linux/err.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/mmc/card.h> |
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#include <linux/mmc/host.h> |
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#include <linux/mmc/slot-gpio.h> |
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#include <linux/gpio/consumer.h> |
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#include "sdhci-pltfm.h" |
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/* Tegra SDHOST controller vendor register definitions */ |
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#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 |
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#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 |
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#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 |
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#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 |
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#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 |
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#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) |
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#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) |
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#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) |
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#define NVQUIRK_DISABLE_SDR50 BIT(3) |
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#define NVQUIRK_DISABLE_SDR104 BIT(4) |
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#define NVQUIRK_DISABLE_DDR50 BIT(5) |
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struct sdhci_tegra_soc_data { |
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const struct sdhci_pltfm_data *pdata; |
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u32 nvquirks; |
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}; |
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struct sdhci_tegra { |
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const struct sdhci_tegra_soc_data *soc_data; |
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struct gpio_desc *power_gpio; |
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}; |
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static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) |
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{ |
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
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struct sdhci_tegra *tegra_host = pltfm_host->priv; |
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
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if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && |
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(reg == SDHCI_HOST_VERSION))) { |
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/* Erratum: Version register is invalid in HW. */ |
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return SDHCI_SPEC_200; |
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} |
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return readw(host->ioaddr + reg); |
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} |
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static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
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{ |
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
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switch (reg) { |
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case SDHCI_TRANSFER_MODE: |
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/* |
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* Postpone this write, we must do it together with a |
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* command write that is down below. |
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*/ |
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pltfm_host->xfer_mode_shadow = val; |
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return; |
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case SDHCI_COMMAND: |
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writel((val << 16) | pltfm_host->xfer_mode_shadow, |
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host->ioaddr + SDHCI_TRANSFER_MODE); |
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return; |
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} |
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writew(val, host->ioaddr + reg); |
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} |
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static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
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{ |
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
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struct sdhci_tegra *tegra_host = pltfm_host->priv; |
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
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/* Seems like we're getting spurious timeout and crc errors, so |
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* disable signalling of them. In case of real errors software |
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* timers should take care of eventually detecting them. |
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*/ |
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if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) |
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val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); |
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writel(val, host->ioaddr + reg); |
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if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && |
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(reg == SDHCI_INT_ENABLE))) { |
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/* Erratum: Must enable block gap interrupt detection */ |
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u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); |
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if (val & SDHCI_INT_CARD_INT) |
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gap_ctrl |= 0x8; |
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else |
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gap_ctrl &= ~0x8; |
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writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); |
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} |
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} |
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static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) |
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{ |
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return mmc_gpio_get_ro(host->mmc); |
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} |
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static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) |
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{ |
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
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struct sdhci_tegra *tegra_host = pltfm_host->priv; |
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; |
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u32 misc_ctrl; |
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sdhci_reset(host, mask); |
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if (!(mask & SDHCI_RESET_ALL)) |
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return; |
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misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); |
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/* Erratum: Enable SDHCI spec v3.00 support */ |
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if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) |
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; |
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/* Don't advertise UHS modes which aren't supported yet */ |
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if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) |
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misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; |
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if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) |
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misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; |
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if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) |
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misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; |
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sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); |
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} |
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static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) |
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{ |
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u32 ctrl; |
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
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if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && |
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(bus_width == MMC_BUS_WIDTH_8)) { |
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ctrl &= ~SDHCI_CTRL_4BITBUS; |
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ctrl |= SDHCI_CTRL_8BITBUS; |
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} else { |
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ctrl &= ~SDHCI_CTRL_8BITBUS; |
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if (bus_width == MMC_BUS_WIDTH_4) |
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ctrl |= SDHCI_CTRL_4BITBUS; |
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else |
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ctrl &= ~SDHCI_CTRL_4BITBUS; |
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} |
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
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} |
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static const struct sdhci_ops tegra_sdhci_ops = { |
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.get_ro = tegra_sdhci_get_ro, |
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.read_w = tegra_sdhci_readw, |
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.write_l = tegra_sdhci_writel, |
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.set_clock = sdhci_set_clock, |
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.set_bus_width = tegra_sdhci_set_bus_width, |
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.reset = tegra_sdhci_reset, |
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.set_uhs_signaling = sdhci_set_uhs_signaling, |
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.get_max_clock = sdhci_pltfm_clk_get_max_clock, |
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}; |
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static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { |
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
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SDHCI_QUIRK_SINGLE_POWER_WRITE | |
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SDHCI_QUIRK_NO_HISPD_BIT | |
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
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.ops = &tegra_sdhci_ops, |
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}; |
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static struct sdhci_tegra_soc_data soc_data_tegra20 = { |
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.pdata = &sdhci_tegra20_pdata, |
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.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | |
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NVQUIRK_ENABLE_BLOCK_GAP_DET, |
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}; |
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static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { |
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
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SDHCI_QUIRK_SINGLE_POWER_WRITE | |
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SDHCI_QUIRK_NO_HISPD_BIT | |
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
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.ops = &tegra_sdhci_ops, |
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}; |
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static struct sdhci_tegra_soc_data soc_data_tegra30 = { |
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.pdata = &sdhci_tegra30_pdata, |
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.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | |
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NVQUIRK_DISABLE_SDR50 | |
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NVQUIRK_DISABLE_SDR104, |
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}; |
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static const struct sdhci_ops tegra114_sdhci_ops = { |
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.get_ro = tegra_sdhci_get_ro, |
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.read_w = tegra_sdhci_readw, |
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.write_w = tegra_sdhci_writew, |
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.write_l = tegra_sdhci_writel, |
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.set_clock = sdhci_set_clock, |
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.set_bus_width = tegra_sdhci_set_bus_width, |
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.reset = tegra_sdhci_reset, |
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.set_uhs_signaling = sdhci_set_uhs_signaling, |
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.get_max_clock = sdhci_pltfm_clk_get_max_clock, |
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}; |
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static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { |
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
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SDHCI_QUIRK_SINGLE_POWER_WRITE | |
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SDHCI_QUIRK_NO_HISPD_BIT | |
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
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.ops = &tegra114_sdhci_ops, |
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}; |
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static struct sdhci_tegra_soc_data soc_data_tegra114 = { |
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.pdata = &sdhci_tegra114_pdata, |
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.nvquirks = NVQUIRK_DISABLE_SDR50 | |
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NVQUIRK_DISABLE_DDR50 | |
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NVQUIRK_DISABLE_SDR104, |
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}; |
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static const struct of_device_id sdhci_tegra_dt_match[] = { |
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{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, |
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{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, |
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{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, |
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{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); |
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static int sdhci_tegra_probe(struct platform_device *pdev) |
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{ |
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const struct of_device_id *match; |
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const struct sdhci_tegra_soc_data *soc_data; |
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struct sdhci_host *host; |
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struct sdhci_pltfm_host *pltfm_host; |
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struct sdhci_tegra *tegra_host; |
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struct clk *clk; |
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int rc; |
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match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); |
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if (!match) |
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return -EINVAL; |
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soc_data = match->data; |
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host = sdhci_pltfm_init(pdev, soc_data->pdata, 0); |
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if (IS_ERR(host)) |
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return PTR_ERR(host); |
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pltfm_host = sdhci_priv(host); |
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tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); |
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if (!tegra_host) { |
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dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); |
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rc = -ENOMEM; |
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goto err_alloc_tegra_host; |
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} |
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tegra_host->soc_data = soc_data; |
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pltfm_host->priv = tegra_host; |
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rc = mmc_of_parse(host->mmc); |
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if (rc) |
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goto err_parse_dt; |
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tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", |
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GPIOD_OUT_HIGH); |
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if (IS_ERR(tegra_host->power_gpio)) { |
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rc = PTR_ERR(tegra_host->power_gpio); |
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goto err_power_req; |
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} |
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clk = devm_clk_get(mmc_dev(host->mmc), NULL); |
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if (IS_ERR(clk)) { |
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dev_err(mmc_dev(host->mmc), "clk err\n"); |
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rc = PTR_ERR(clk); |
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goto err_clk_get; |
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} |
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clk_prepare_enable(clk); |
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pltfm_host->clk = clk; |
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rc = sdhci_add_host(host); |
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if (rc) |
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goto err_add_host; |
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return 0; |
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err_add_host: |
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clk_disable_unprepare(pltfm_host->clk); |
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err_clk_get: |
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err_power_req: |
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err_parse_dt: |
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err_alloc_tegra_host: |
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sdhci_pltfm_free(pdev); |
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return rc; |
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} |
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static struct platform_driver sdhci_tegra_driver = { |
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.driver = { |
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.name = "sdhci-tegra", |
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.of_match_table = sdhci_tegra_dt_match, |
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.pm = SDHCI_PLTFM_PMOPS, |
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}, |
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.probe = sdhci_tegra_probe, |
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.remove = sdhci_pltfm_unregister, |
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}; |
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module_platform_driver(sdhci_tegra_driver); |
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MODULE_DESCRIPTION("SDHCI driver for Tegra"); |
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MODULE_AUTHOR("Google, Inc."); |
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MODULE_LICENSE("GPL v2");
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