/* * Copyright (c) 2014 MediaTek Inc. * Author: Roy Chen * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef _DT_BINDINGS_CLK_MT6763_H #define _DT_BINDINGS_CLK_MT6763_H /* TOPCKGEN */ #define TOP_MUX_AXI 1 #define TOP_MUX_MM 2 #define TOP_MUX_PWM 3 #define TOP_MUX_CAM 4 #define TOP_MUX_VENC 5 #define TOP_MUX_MFG 6 #define TOP_MUX_CAMTG 7 #define TOP_MUX_UART 8 #define TOP_MUX_SPI 9 #define TOP_MUX_USB20 10 #define TOP_MUX_MSDC50_0_HCLK 11 #define TOP_MUX_MSDC50_0 12 #define TOP_MUX_MSDC30_1 13 #define TOP_MUX_MSDC30_2 14 #define TOP_MUX_MSDC30_3 15 #define TOP_MUX_AUDIO 16 #define TOP_MUX_AUD_INTBUS 17 #define TOP_MUX_FPWRAP_ULPOSC 18 #define TOP_MUX_SCP 19 #define TOP_MUX_ATB 20 #define TOP_MUX_SSPM 21 #define TOP_MUX_DPI0 22 #define TOP_MUX_SCAM 23 #define TOP_MUX_AUD_1 24 #define TOP_MUX_AUD_2 25 #define TOP_MUX_DISP_PWM 26 #define TOP_MUX_SSUSB_TOP_SYS 27 #define TOP_MUX_SSUSB_TOP_XHCI 28 #define TOP_MUX_USB_TOP 29 #define TOP_MUX_SPM 30 #define TOP_MUX_I2C 31 #define TOP_MUX_F52M_MFG 32 #define TOP_MUX_SENINF 33 #define TOP_MUX_DXCC 34 #define TOP_MUX_CAMTG2 35 #define TOP_MUX_AUD_ENG1 36 #define TOP_MUX_AUD_ENG2 37 #define TOP_MUX_FAES_UFSFDE 38 #define TOP_MUX_FUFS 39 #define TOP_SYSPLL_CK 40 #define TOP_SYSPLL_D2 41 #define TOP_SYSPLL_D3 42 #define TOP_SYSPLL_D3_D3 43 #define TOP_SYSPLL_D5 44 #define TOP_SYSPLL_D7 45 #define TOP_SYSPLL1_D2 46 #define TOP_SYSPLL1_D4 47 #define TOP_SYSPLL1_D8 48 #define TOP_SYSPLL1_D16 49 #define TOP_SYSPLL2_D2 50 #define TOP_SYSPLL2_D4 51 #define TOP_SYSPLL2_D8 52 #define TOP_SYSPLL3_D2 53 #define TOP_SYSPLL3_D4 54 #define TOP_SYSPLL4_D2 55 #define TOP_SYSPLL4_D4 56 #define TOP_UNIVPLL_CK 57 #define TOP_UNIVPLL_D2 58 #define TOP_UNIVPLL_D3 59 #define TOP_UNIVPLL_D5 60 #define TOP_UNIVPLL_D7 61 #define TOP_UNIVPLL_D26 62 #define TOP_UNIVPLL_D52 63 #define TOP_UNIVPLL_D104 64 #define TOP_UNIVPLL_D208 65 #define TOP_UNIVPLL1_D2 66 #define TOP_UNIVPLL1_D4 67 #define TOP_UNIVPLL1_D8 68 #define TOP_UNIVPLL2_D2 69 #define TOP_UNIVPLL2_D4 70 #define TOP_UNIVPLL2_D8 71 #define TOP_UNIVPLL2_D16 72 #define TOP_UNIVPLL2_D32 73 #define TOP_UNIVPLL3_D2 74 #define TOP_UNIVPLL3_D4 75 #define TOP_UNIVPLL3_D8 76 #define TOP_APLL1_CK 77 #define TOP_APLL1_D2 78 #define TOP_APLL1_D4 79 #define TOP_APLL1_D8 80 #define TOP_APLL2_CK 81 #define TOP_APLL2_D2 82 #define TOP_APLL2_D4 83 #define TOP_APLL2_D8 84 #define TOP_TVDPLL_CK 85 #define TOP_TVDPLL_D2 86 #define TOP_TVDPLL_D4 87 #define TOP_TVDPLL_D8 88 #define TOP_TVDPLL_D16 89 #define TOP_MSDCPLL_CK 90 #define TOP_MSDCPLL_D2 91 #define TOP_MSDCPLL_D4 92 #define TOP_MSDCPLL_D8 93 #define TOP_MSDCPLL_D16 94 #define TOP_AD_OSC_CK 95 #define TOP_OSC_D2 96 #define TOP_OSC_D4 97 #define TOP_OSC_D8 98 #define TOP_OSC_D16 99 #define TOP_OSC_D32 100 #define TOP_VENCPLL_CK 101 #define TOP_MMPLL_CK 102 #define TOP_MFGPLL_CK 103 #define TOP_CLK_NULL 104 #define TOP_CLK32K 105 #define TOP_CLK26M 106 #define TOP_CLK13M 107 #define TOP_NR_CLK 108 /* APMIXED */ #define APMIXED_ARMPLL_LL 1 #define APMIXED_ARMPLL_L 2 #define APMIXED_CCIPLL 3 #define APMIXED_MAINPLL 4 #define APMIXED_UNIVPLL 5 #define APMIXED_MSDCPLL 6 #define APMIXED_MMPLL 7 #define APMIXED_MFGPLL 8 #define APMIXED_TVDPLL 9 #define APMIXED_APLL1 10 #define APMIXED_APLL2 11 #define SCP_OSCPLL 12 #define APMIXED_NR_CLK 13 /* CAMSYS */ #define CAMSYS_LARB2_CGPDN 1 #define CAMSYS_DFP_VAD_CGPDN 2 #define CAMSYS_CAM_CGPDN 3 #define CAMSYS_CAMTG_CGPDN 4 #define CAMSYS_SENINF_CGPDN 5 #define CAMSYS_CAMSV0_CGPDN 6 #define CAMSYS_CAMSV1_CGPDN 7 #define CAMSYS_CAMSV2_CGPDN 8 #define CAMSYS_CCU_CGPDN 9 #define CAMSYS_NR_CLK 10 /* INFRACFG_AO */ #define INFRACFG_AO_PMIC_CG_TMR 1 #define INFRACFG_AO_PMIC_CG_AP 2 #define INFRACFG_AO_PMIC_CG_MD 3 #define INFRACFG_AO_PMIC_CG_CONN 4 #define INFRACFG_AO_SCPSYS_CG 5 #define INFRACFG_AO_SEJ_CG 6 #define INFRACFG_AO_APXGPT_CG 7 #define INFRACFG_AO_ICUSB_CG 8 #define INFRACFG_AO_GCE_CG 9 #define INFRACFG_AO_THERM_CG 10 #define INFRACFG_AO_I2C0_CG 11 #define INFRACFG_AO_I2C1_CG 12 #define INFRACFG_AO_I2C2_CG 13 #define INFRACFG_AO_I2C3_CG 14 #define INFRACFG_AO_PWM_HCLK_CG 15 #define INFRACFG_AO_PWM1_CG 16 #define INFRACFG_AO_PWM2_CG 17 #define INFRACFG_AO_PWM3_CG 18 #define INFRACFG_AO_PWM4_CG 19 #define INFRACFG_AO_PWM_CG 20 #define INFRACFG_AO_UART0_CG 21 #define INFRACFG_AO_UART1_CG 22 #define INFRACFG_AO_UART2_CG 23 #define INFRACFG_AO_UART3_CG 24 #define INFRACFG_AO_GCE_26M_CG 25 #define INFRACFG_AO_CQ_DMA_FPC_CG 26 #define INFRACFG_AO_BTIF_CG 27 #define INFRACFG_AO_SPI0_CG 28 #define INFRACFG_AO_MSDC0_CG 29 #define INFRACFG_AO_MSDC1_CG 30 #define INFRACFG_AO_MSDC2_CG 31 #define INFRACFG_AO_MSDC0_SCK_CG 32 #define INFRACFG_AO_DVFSRC_CG 33 #define INFRACFG_AO_GCPU_CG 34 #define INFRACFG_AO_TRNG_CG 35 #define INFRACFG_AO_AUXADC_CG 36 #define INFRACFG_AO_CPUM_CG 37 #define INFRACFG_AO_CCIF1_AP_CG 38 #define INFRACFG_AO_CCIF1_MD_CG 39 #define INFRACFG_AO_AUXADC_MD_CG 40 #define INFRACFG_AO_MSDC1_SCK_CG 41 #define INFRACFG_AO_MSDC2_SCK_CG 42 #define INFRACFG_AO_AP_DMA_CG 43 #define INFRACFG_AO_XIU_CG 44 #define INFRACFG_AO_DEVICE_APC_CG 45 #define INFRACFG_AO_CCIF_AP_CG 46 #define INFRACFG_AO_DEBUGSYS_CG 47 #define INFRACFG_AO_AUDIO_CG 48 #define INFRACFG_AO_CCIF_MD_CG 49 #define INFRACFG_AO_DXCC_SEC_CORE_CG 50 #define INFRACFG_AO_DXCC_AO_CG 51 #define INFRACFG_AO_DRAMC_F26M_CG 52 #define INFRACFG_AO_IRTX_CG 53 #define INFRACFG_AO_DISP_PWM_CG 54 #define INFRACFG_AO_CLDMA_BCLK_CK 55 #define INFRACFG_AO_AUDIO_26M_BCLK_CK 56 #define INFRACFG_AO_SPI1_CG 57 #define INFRACFG_AO_I2C4_CG 58 #define INFRACFG_AO_MODEM_TEMP_SHARE_CG 59 #define INFRACFG_AO_SPI2_CG 60 #define INFRACFG_AO_SPI3_CG 61 #define INFRACFG_AO_UNIPRO_SCK_CG 62 #define INFRACFG_AO_UNIPRO_TICK_CG 63 #define INFRACFG_AO_UFS_MP_SAP_BCLK_CG 64 #define INFRACFG_AO_MD32_BCLK_CG 65 #define INFRACFG_AO_SSPM_CG 66 #define INFRACFG_AO_UNIPRO_MBIST_CG 67 #define INFRACFG_AO_SSPM_BUS_HCLK_CG 68 #define INFRACFG_AO_I2C5_CG 69 #define INFRACFG_AO_I2C5_ARBITER_CG 70 #define INFRACFG_AO_I2C5_IMM_CG 71 #define INFRACFG_AO_I2C1_ARBITER_CG 72 #define INFRACFG_AO_I2C1_IMM_CG 73 #define INFRACFG_AO_I2C2_ARBITER_CG 74 #define INFRACFG_AO_I2C2_IMM_CG 75 #define INFRACFG_AO_SPI4_CG 76 #define INFRACFG_AO_SPI5_CG 77 #define INFRACFG_AO_CQ_DMA_CG 78 #define INFRACFG_AO_UFS_CG 79 #define INFRACFG_AO_AES_CG 80 #define INFRACFG_AO_UFS_TICK_CG 81 #define INFRACFG_AO_MSDC0_SELF_CG 82 #define INFRACFG_AO_MSDC1_SELF_CG 83 #define INFRACFG_AO_MSDC2_SELF_CG 84 #define INFRACFG_AO_SSPM_26M_SELF_CG 85 #define INFRACFG_AO_SSPM_32K_SELF_CG 86 #define INFRACFG_AO_UFS_AXI_CG 87 #define INFRACFG_AO_I2C6_CG 88 #define INFRACFG_AO_AP_MSDC0_CG 89 #define INFRACFG_AO_MD_MSDC0_CG 90 #define INFRACFG_AO_NR_CLK 91 /* MFGCFG */ #define MFGCFG_BG3D 1 #define MFGCFG_NR_CLK 2 /* IMG */ #define IMG_RSC 1 #define IMG_GEPF 2 #define IMG_FDVT 3 #define IMG_DPE 4 #define IMG_DIP 5 #define IMG_DFP_VAD 6 #define IMG_LARB5 7 #define IMG_NR_CLK 8 /* MMSYS_CONFIG */ #define MMSYS_SMI_COMMON 1 #define MMSYS_SMI_LARB0 2 #define MMSYS_SMI_LARB1 3 #define MMSYS_GALS_COMM0 4 #define MMSYS_GALS_COMM1 5 #define MMSYS_GALS_VENC2MM 6 #define MMSYS_GALS_VDEC2MM 7 #define MMSYS_GALS_IMG2MM 8 #define MMSYS_GALS_CAM2MM 9 #define MMSYS_GALS_IPU2MM 10 #define MMSYS_MDP_DL_TXCK 11 #define MMSYS_IPU_DL_TXCK 12 #define MMSYS_MDP_RDMA0 13 #define MMSYS_MDP_RDMA1 14 #define MMSYS_MDP_RSZ0 15 #define MMSYS_MDP_RSZ1 16 #define MMSYS_MDP_TDSHP 17 #define MMSYS_MDP_WROT0 18 #define MMSYS_MDP_WDMA 19 #define MMSYS_FAKE_ENG 20 #define MMSYS_DISP_OVL0 21 #define MMSYS_DISP_OVL0_2L 22 #define MMSYS_DISP_OVL1_2L 23 #define MMSYS_DISP_RDMA0 24 #define MMSYS_DISP_RDMA1 25 #define MMSYS_DISP_WDMA0 26 #define MMSYS_DISP_COLOR0 27 #define MMSYS_DISP_CCORR0 28 #define MMSYS_DISP_AAL0 29 #define MMSYS_DISP_GAMMA0 30 #define MMSYS_DISP_DITHER0 31 #define MMSYS_DISP_SPLIT 32 #define MMSYS_DSI0_MM_CK 33 #define MMSYS_DSI0_IF_CK 34 #define MMSYS_DPI_MM_CK 35 #define MMSYS_DPI_IF_CK 36 #define MMSYS_FAKE_ENG2 37 #define MMSYS_MDP_DL_RX_CK 38 #define MMSYS_IPU_DL_RX_CK 39 #define MMSYS_26M 40 #define MMSYS_MMSYS_R2Y 41 #define MMSYS_DISP_RSZ 42 #define MMSYS_CONFIG_NR_CLK 43 /* VDEC_GCON */ #define VDEC_VDEC 1 #define VDEC_LARB1 2 #define VDEC_GCON_NR_CLK 3 /* VENC_GCON */ #define VENC_GCON_LARB 1 #define VENC_GCON_VENC 2 #define VENC_GCON_JPGENC 3 #define VENC_GCON_VDEC 4 #define VENC_GCON_NR_CLK 5 /* AUDIO */ #define AUDIO_TML 1 #define AUDIO_DAC_PREDIS 2 #define AUDIO_DAC 3 #define AUDIO_ADC 4 #define AUDIO_APLL_TUNER 5 #define AUDIO_APLL2_TUNER 6 #define AUDIO_24M 7 #define AUDIO_22M 8 #define AUDIO_I2S 9 #define AUDIO_AFE 10 #define AUDIO_I2S4_BCLK_SW 11 #define AUDIO_I2S3_BCLK_SW 12 #define AUDIO_I2S2_BCLK_SW 13 #define AUDIO_I2S1_BCLK_SW 14 #define AUDIO_NR_CLK 15 /* SCP_SYS */ #define SCP_SYS_MD1 1 #define SCP_SYS_CONN 2 #define SCP_SYS_DIS 3 #define SCP_SYS_MFG 4 #define SCP_SYS_ISP 5 #define SCP_SYS_VEN 6 #define SCP_SYS_MFG_ASYNC 7 #define SCP_SYS_AUDIO 8 #define SCP_SYS_CAM 9 #define SCP_SYS_MFG_CORE1 10 #define SCP_SYS_MFG_CORE0 11 #define SCP_NR_SYSS 12 #endif /* _DT_BINDINGS_CLK_MT6763_H */