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265 lines
8.3 KiB
265 lines
8.3 KiB
/* |
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* Copyright (C) 2012,2014 The Android Open Source Project |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); |
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* you may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0 |
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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/* |
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x0 = dst |
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x1 = y0 base pointer |
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x2 = y1 base pointer |
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x3 = y2 base pointer |
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x4 = coeffs |
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x5 = length / 2 |
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*/ |
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#define ENTRY(f) .text; .align 2; .globl f; .type f,#function; f: |
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#define END(f) .size f, .-f; |
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ENTRY(rsdIntrinsicConvolve3x3_K) |
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sub x6, sp, #64 |
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sub sp, sp, #64 |
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st1 {v8.1d-v11.1d}, [x6], #32 |
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st1 {v12.1d-v15.1d}, [x6] |
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/* Load the coefficients in the v0, v1 registers */ |
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ld1 {v0.8h, v1.8h}, [x4] |
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/* Load the frequently used immediate in a register */ |
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mov x4, #8 |
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1: |
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/* Load and post-increase the address by x4=#8 */ |
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ld1 {v13.16b}, [x1], x4 |
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ld1 {v14.16b}, [x2], x4 |
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ld1 {v15.16b}, [x3], x4 |
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/* Signal memory for data that will be used in the loop after the next */ |
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// prfm PLDL1KEEP,[x1, x4] // TODO: test this |
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// prfm PLDL1KEEP,[x2, x4] // TODO: test this |
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// prfm PLDL1KEEP,[x3, x4] // TODO: test this |
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uxtl v2.8h, v13.8b |
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uxtl2 v3.8h, v13.16b |
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uxtl v4.8h, v14.8b |
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uxtl2 v5.8h, v14.16b |
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uxtl v6.8h, v15.8b |
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uxtl2 v7.8h, v15.16b |
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/* |
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The two pixel source array is |
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v2, v2hi, v3lo, v3hi |
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v4, v4hi, v5lo, v5hi |
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v6, v6hi, v7lo, v7hi |
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*/ |
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smull v8.4s, v2.4h, v0.h[0] |
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smull2 v9.4s, v2.8h, v0.h[0] |
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smlal2 v8.4s, v2.8h, v0.h[1] |
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smlal v9.4s, v3.4h, v0.h[1] |
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smlal v8.4s, v3.4h, v0.h[2] |
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smlal2 v9.4s, v3.8h, v0.h[2] |
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smlal v8.4s, v4.4h, v0.h[3] |
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smlal2 v9.4s, v4.8h, v0.h[3] |
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smlal2 v8.4s, v4.8h, v0.h[4] |
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smlal v9.4s, v5.4h, v0.h[4] |
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smlal v8.4s, v5.4h, v0.h[5] |
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smlal2 v9.4s, v5.8h, v0.h[5] |
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smlal v8.4s, v6.4h, v0.h[6] |
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smlal2 v9.4s, v6.8h, v0.h[6] |
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smlal2 v8.4s, v6.8h, v0.h[7] |
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smlal v9.4s, v7.4h, v0.h[7] |
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smlal v8.4s, v7.4h, v1.h[0] |
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smlal2 v9.4s, v7.8h, v1.h[0] |
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shrn v8.4h, v8.4s, #8 |
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shrn2 v8.8h, v9.4s, #8 |
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sqxtun v8.8b, v8.8h |
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st1 {v8.8b}, [x0], #8 |
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/* Are we done yet? */ |
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subs x5, x5, #1 |
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bne 1b |
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/* We're done, bye! */ |
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ld1 {v8.1d-v11.1d}, [sp], #32 |
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ld1 {v12.1d-v15.1d}, [sp], #32 |
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ret |
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END(rsdIntrinsicConvolve3x3_K) |
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/* Convolve 5x5 */ |
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/* |
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x0 = dst |
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x1 = y0 base pointer |
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x2 = y1 base pointer |
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x3 = y2 base pointer |
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x4 = y3 base pointer |
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x5 = y4 base pointer |
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x6 = coeffs |
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x7 = length |
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*/ |
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ENTRY(rsdIntrinsicConvolve5x5_K) |
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sub x8, sp, #64 |
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sub sp, sp, #64 |
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st1 {v8.1d-v11.1d}, [x8], #32 |
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st1 {v12.1d-v15.1d}, [x8] |
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/* Create the coefficients vector */ |
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ld1 {v0.8h-v2.8h}, [x6], #48 |
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ld1 {v3.4h}, [x6], #8 |
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movi v15.4s, #0x7f |
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/* Load the frequently used immediate in a register */ |
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mov x6, #8 |
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1: |
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/* Load the y base pointers in Qregs and post-increase the address by x6=#8 */ |
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ld1 {v9.8b-v11.8b}, [x1], x6 // y0 ( y - 2 ) |
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ld1 {v12.8b-v14.8b}, [x2], x6 // y0 ( y - 1 ) |
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/* Signal memory for data that will be used in the loop after the next */ |
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// prfm PLDL1KEEP,[x1, x6] // TODO: test this |
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// prfm PLDL1KEEP,[x2, x6] // TODO: test this |
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/* Promoting the 8bit channels to 16bit */ |
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uxtl v9.8h, v9.8b |
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uxtl v10.8h, v10.8b |
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uxtl v11.8h, v11.8b |
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uxtl v12.8h, v12.8b |
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uxtl v13.8h, v13.8b |
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uxtl v14.8h, v14.8b |
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/* |
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v9, v9hi, v10lo, v10hi, v11lo, v11hi, |
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v12, v12hi |
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*/ |
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smull v4.4s, v9.4h, v0.h[0] |
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smull2 v5.4s, v9.8h, v0.h[0] |
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smlal2 v4.4s, v9.8h, v0.h[1] |
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smlal v5.4s, v10.4h, v0.h[1] |
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smlal v4.4s, v10.4h, v0.h[2] |
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smlal2 v5.4s, v10.8h, v0.h[2] |
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smlal2 v4.4s, v10.8h, v0.h[3] |
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smlal v5.4s, v11.4h, v0.h[3] |
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smlal v4.4s, v11.4h, v0.h[4] |
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smlal2 v5.4s, v11.8h, v0.h[4] |
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smlal v4.4s, v12.4h, v0.h[5] |
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smlal2 v5.4s, v12.8h, v0.h[5] |
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smlal2 v4.4s, v12.8h, v0.h[6] |
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smlal v5.4s, v13.4h, v0.h[6] |
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smlal v4.4s, v13.4h, v0.h[7] |
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smlal2 v5.4s, v13.8h, v0.h[7] |
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smlal2 v4.4s, v13.8h, v1.h[0] |
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smlal v5.4s, v14.4h, v1.h[0] |
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smlal v4.4s, v14.4h, v1.h[1] |
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smlal2 v5.4s, v14.8h, v1.h[1] |
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/* Next 2 rows */ |
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/* Load the y base pointers in Qregs and post-increase the address by x6=#8 */ |
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ld1 {v9.8b-v11.8b}, [x3], x6 // y0 ( y ) |
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ld1 {v12.8b-v14.8b}, [x4], x6 // y0 ( y + 1 ) |
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/* Signal memory for data that will be used in the loop after the next */ |
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// prfm PLDL1KEEP,[x3, x6] // TODO: test this |
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// prfm PLDL1KEEP,[x4, x6] // TODO: test this |
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/* Promoting the 8bit channels to 16bit */ |
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uxtl v9.8h, v9.8b |
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uxtl v10.8h, v10.8b |
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uxtl v11.8h, v11.8b |
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uxtl v12.8h, v12.8b |
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uxtl v13.8h, v13.8b |
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uxtl v14.8h, v14.8b |
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/* |
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v9, v9hi, v10lo, v10hi, v11lo, v11hi, |
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v12, v12hi |
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*/ |
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smlal v4.4s, v9.4h, v1.h[2] |
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smlal2 v5.4s, v9.8h, v1.h[2] |
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smlal2 v4.4s, v9.8h, v1.h[3] |
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smlal v5.4s, v10.4h, v1.h[3] |
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smlal v4.4s, v10.4h, v1.h[4] |
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smlal2 v5.4s, v10.8h, v1.h[4] |
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smlal2 v4.4s, v10.8h, v1.h[5] |
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smlal v5.4s, v11.4h, v1.h[5] |
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smlal v4.4s, v11.4h, v1.h[6] |
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smlal2 v5.4s, v11.8h, v1.h[6] |
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smlal v4.4s, v12.4h, v1.h[7] |
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smlal2 v5.4s, v12.8h, v1.h[7] |
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smlal2 v4.4s, v12.8h, v2.h[0] |
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smlal v5.4s, v13.4h, v2.h[0] |
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smlal v4.4s, v13.4h, v2.h[1] |
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smlal2 v5.4s, v13.8h, v2.h[1] |
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smlal2 v4.4s, v13.8h, v2.h[2] |
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smlal v5.4s, v14.4h, v2.h[2] |
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smlal v4.4s, v14.4h, v2.h[3] |
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smlal2 v5.4s, v14.8h, v2.h[3] |
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/* Last row */ |
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/* Load the y base pointers in Qregs and post-increase the address by x6=#8 */ |
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ld1 {v9.8b- v11.8b}, [x5], x6 // y0 ( y + 2 ) |
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/* Signal memory for data that will be used in the loop after the next */ |
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// prfm PLDL1KEEP,[x5, x6] // TODO: test this |
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/* Promoting the 8bit channels to 16bit */ |
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uxtl v9.8h, v9.8b |
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uxtl v10.8h, v10.8b |
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uxtl v11.8h, v11.8b |
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/* |
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v9, v9hi, v10lo, v10hi, v11lo, v11hi, |
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v12, v12hi |
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*/ |
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smlal v4.4s, v9.4h, v2.h[4] |
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smlal2 v5.4s, v9.8h, v2.h[4] |
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smlal2 v4.4s, v9.8h, v2.h[5] |
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smlal v5.4s, v10.4h, v2.h[5] |
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smlal v4.4s, v10.4h, v2.h[6] |
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smlal2 v5.4s, v10.8h, v2.h[6] |
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smlal2 v4.4s, v10.8h, v2.h[7] |
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smlal v5.4s, v11.4h, v2.h[7] |
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smlal v4.4s, v11.4h, v3.h[0] |
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smlal2 v5.4s, v11.8h, v3.h[0] |
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add v4.4s, v4.4s, v15.4s |
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add v5.4s, v5.4s, v15.4s |
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/* Narrow it to a d-reg 32 -> 16 bit */ |
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rshrn v4.4h, v4.4s, #8 |
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rshrn2 v4.8h, v5.4s, #8 |
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/* Pack 16 -> 8 bit, saturate, put two pixels into D reg */ |
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sqxtun v4.8b, v4.8h |
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st1 {v4.8b}, [x0], #8 // return the output and increase the address of x0 |
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/* Are we done? */ |
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subs x7, x7, #1 |
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bne 1b |
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/* Yup, bye */ |
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ld1 {v8.1d-v11.1d}, [sp], #32 |
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ld1 {v12.1d-v15.1d}, [sp], #32 |
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ret |
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END(rsdIntrinsicConvolve5x5_K)
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