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125 lines
3.8 KiB
125 lines
3.8 KiB
/* |
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* bfin_crc.h - interface to Blackfin CRC controllers |
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* |
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* Copyright 2012 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#ifndef __BFIN_CRC_H__ |
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#define __BFIN_CRC_H__ |
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/* Function driver which use hardware crc must initialize the structure */ |
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struct crc_info { |
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/* Input data address */ |
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unsigned char *in_addr; |
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/* Output data address */ |
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unsigned char *out_addr; |
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/* Input or output bytes */ |
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unsigned long datasize; |
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union { |
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/* CRC to compare with that of input buffer */ |
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unsigned long crc_compare; |
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/* Value to compare with input data */ |
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unsigned long val_verify; |
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/* Value to fill */ |
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unsigned long val_fill; |
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}; |
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/* Value to program the 32b CRC Polynomial */ |
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unsigned long crc_poly; |
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union { |
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/* CRC calculated from the input data */ |
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unsigned long crc_result; |
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/* First failed position to verify input data */ |
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unsigned long pos_verify; |
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}; |
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/* CRC mirror flags */ |
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unsigned int bitmirr:1; |
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unsigned int bytmirr:1; |
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unsigned int w16swp:1; |
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unsigned int fdsel:1; |
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unsigned int rsltmirr:1; |
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unsigned int polymirr:1; |
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unsigned int cmpmirr:1; |
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}; |
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/* Userspace interface */ |
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#define CRC_IOC_MAGIC 'C' |
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#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int) |
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#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int) |
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#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int) |
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#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int) |
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#ifdef __KERNEL__ |
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#include <linux/types.h> |
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#include <linux/spinlock.h> |
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#include <linux/miscdevice.h> |
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struct crc_register { |
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u32 control; |
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u32 datacnt; |
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u32 datacntrld; |
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u32 __pad_1[2]; |
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u32 compare; |
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u32 fillval; |
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u32 datafifo; |
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u32 intren; |
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u32 intrenset; |
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u32 intrenclr; |
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u32 poly; |
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u32 __pad_2[4]; |
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u32 status; |
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u32 datacntcap; |
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u32 __pad_3; |
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u32 result; |
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u32 curresult; |
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u32 __pad_4[3]; |
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u32 revid; |
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}; |
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/* CRC_STATUS Masks */ |
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#define CMPERR 0x00000002 /* Compare error */ |
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#define DCNTEXP 0x00000010 /* datacnt register expired */ |
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#define IBR 0x00010000 /* Input buffer ready */ |
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#define OBR 0x00020000 /* Output buffer ready */ |
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#define IRR 0x00040000 /* Immediate result readt */ |
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#define LUTDONE 0x00080000 /* Look-up table generation done */ |
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#define FSTAT 0x00700000 /* FIFO status */ |
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#define MAX_FIFO 4 /* Max fifo size */ |
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/* CRC_CONTROL Masks */ |
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#define BLKEN 0x00000001 /* Block enable */ |
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#define OPMODE 0x000000F0 /* Operation mode */ |
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#define OPMODE_OFFSET 4 /* Operation mode mask offset*/ |
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#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */ |
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#define MODE_DATA_FILL 2 /* MTM data fill */ |
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#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */ |
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#define MODE_DATA_VERIFY 4 /* MSM data verify */ |
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#define AUTOCLRZ 0x00000100 /* Auto clear to zero */ |
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#define AUTOCLRF 0x00000200 /* Auto clear to one */ |
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#define OBRSTALL 0x00001000 /* Stall on output buffer ready */ |
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#define IRRSTALL 0x00002000 /* Stall on immediate result ready */ |
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#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */ |
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#define BITMIRR_OFFSET 16 /* Mirror bits offset */ |
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#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */ |
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#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */ |
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#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */ |
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#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */ |
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#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */ |
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#define FDSEL_OFFSET 19 /* Mirror FIFO offset */ |
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#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */ |
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#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */ |
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#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */ |
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#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */ |
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#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */ |
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#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */ |
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/* CRC_INTREN Masks */ |
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#define CMPERRI 0x02 /* CRC_ERROR_INTR */ |
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#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */ |
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#endif |
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#endif
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