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223 lines
4.3 KiB
223 lines
4.3 KiB
/* |
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* 440SPe's DMA engines support header file |
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* |
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* 2006-2009 (C) DENX Software Engineering. |
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* |
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* Author: Yuri Tikhonov <yur@emcraft.com> |
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* |
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* This file is licensed under the term of the GNU General Public License |
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* version 2. The program licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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#ifndef _PPC440SPE_DMA_H |
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#define _PPC440SPE_DMA_H |
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#include <linux/types.h> |
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/* Number of elements in the array with statical CDBs */ |
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#define MAX_STAT_DMA_CDBS 16 |
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/* Number of DMA engines available on the contoller */ |
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#define DMA_ENGINES_NUM 2 |
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/* Maximum h/w supported number of destinations */ |
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#define DMA_DEST_MAX_NUM 2 |
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/* FIFO's params */ |
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#define DMA0_FIFO_SIZE 0x1000 |
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#define DMA1_FIFO_SIZE 0x1000 |
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#define DMA_FIFO_ENABLE (1<<12) |
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/* DMA Configuration Register. Data Transfer Engine PLB Priority: */ |
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#define DMA_CFG_DXEPR_LP (0<<26) |
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#define DMA_CFG_DXEPR_HP (3<<26) |
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#define DMA_CFG_DXEPR_HHP (2<<26) |
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#define DMA_CFG_DXEPR_HHHP (1<<26) |
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/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */ |
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#define DMA_CFG_DFMPP_LP (0<<23) |
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#define DMA_CFG_DFMPP_HP (3<<23) |
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#define DMA_CFG_DFMPP_HHP (2<<23) |
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#define DMA_CFG_DFMPP_HHHP (1<<23) |
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/* DMA Configuration Register. Force 64-byte Alignment */ |
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#define DMA_CFG_FALGN (1 << 19) |
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/*UIC0:*/ |
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#define D0CPF_INT (1<<12) |
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#define D0CSF_INT (1<<11) |
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#define D1CPF_INT (1<<10) |
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#define D1CSF_INT (1<<9) |
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/*UIC1:*/ |
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#define DMAE_INT (1<<9) |
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/* I2O IOP Interrupt Mask Register */ |
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#define I2O_IOPIM_P0SNE (1<<3) |
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#define I2O_IOPIM_P0EM (1<<5) |
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#define I2O_IOPIM_P1SNE (1<<6) |
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#define I2O_IOPIM_P1EM (1<<8) |
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/* DMA CDB fields */ |
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#define DMA_CDB_MSK (0xF) |
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#define DMA_CDB_64B_ADDR (1<<2) |
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#define DMA_CDB_NO_INT (1<<3) |
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#define DMA_CDB_STATUS_MSK (0x3) |
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#define DMA_CDB_ADDR_MSK (0xFFFFFFF0) |
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/* DMA CDB OpCodes */ |
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#define DMA_CDB_OPC_NO_OP (0x00) |
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#define DMA_CDB_OPC_MV_SG1_SG2 (0x01) |
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#define DMA_CDB_OPC_MULTICAST (0x05) |
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#define DMA_CDB_OPC_DFILL128 (0x24) |
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#define DMA_CDB_OPC_DCHECK128 (0x23) |
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#define DMA_CUED_XOR_BASE (0x10000000) |
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#define DMA_CUED_XOR_HB (0x00000008) |
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#ifdef CONFIG_440SP |
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#define DMA_CUED_MULT1_OFF 0 |
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#define DMA_CUED_MULT2_OFF 8 |
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#define DMA_CUED_MULT3_OFF 16 |
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#define DMA_CUED_REGION_OFF 24 |
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#define DMA_CUED_XOR_WIN_MSK (0xFC000000) |
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#else |
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#define DMA_CUED_MULT1_OFF 2 |
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#define DMA_CUED_MULT2_OFF 10 |
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#define DMA_CUED_MULT3_OFF 18 |
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#define DMA_CUED_REGION_OFF 26 |
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#define DMA_CUED_XOR_WIN_MSK (0xF0000000) |
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#endif |
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#define DMA_CUED_REGION_MSK 0x3 |
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#define DMA_RXOR123 0x0 |
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#define DMA_RXOR124 0x1 |
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#define DMA_RXOR125 0x2 |
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#define DMA_RXOR12 0x3 |
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/* S/G addresses */ |
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#define DMA_CDB_SG_SRC 1 |
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#define DMA_CDB_SG_DST1 2 |
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#define DMA_CDB_SG_DST2 3 |
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/* |
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* DMAx engines Command Descriptor Block Type |
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*/ |
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struct dma_cdb { |
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/* |
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* Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf) |
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*/ |
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u8 pad0[2]; /* reserved */ |
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u8 attr; /* attributes */ |
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u8 opc; /* opcode */ |
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u32 sg1u; /* upper SG1 address */ |
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u32 sg1l; /* lower SG1 address */ |
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u32 cnt; /* SG count, 3B used */ |
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u32 sg2u; /* upper SG2 address */ |
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u32 sg2l; /* lower SG2 address */ |
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u32 sg3u; /* upper SG3 address */ |
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u32 sg3l; /* lower SG3 address */ |
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}; |
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/* |
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* DMAx hardware registers (p.515 in 440SPe UM 1.22) |
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*/ |
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struct dma_regs { |
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u32 cpfpl; |
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u32 cpfph; |
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u32 csfpl; |
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u32 csfph; |
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u32 dsts; |
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u32 cfg; |
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u8 pad0[0x8]; |
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u16 cpfhp; |
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u16 cpftp; |
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u16 csfhp; |
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u16 csftp; |
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u8 pad1[0x8]; |
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u32 acpl; |
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u32 acph; |
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u32 s1bpl; |
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u32 s1bph; |
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u32 s2bpl; |
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u32 s2bph; |
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u32 s3bpl; |
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u32 s3bph; |
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u8 pad2[0x10]; |
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u32 earl; |
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u32 earh; |
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u8 pad3[0x8]; |
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u32 seat; |
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u32 sead; |
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u32 op; |
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u32 fsiz; |
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}; |
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/* |
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* I2O hardware registers (p.528 in 440SPe UM 1.22) |
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*/ |
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struct i2o_regs { |
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u32 ists; |
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u32 iseat; |
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u32 isead; |
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u8 pad0[0x14]; |
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u32 idbel; |
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u8 pad1[0xc]; |
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u32 ihis; |
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u32 ihim; |
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u8 pad2[0x8]; |
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u32 ihiq; |
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u32 ihoq; |
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u8 pad3[0x8]; |
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u32 iopis; |
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u32 iopim; |
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u32 iopiq; |
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u8 iopoq; |
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u8 pad4[3]; |
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u16 iiflh; |
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u16 iiflt; |
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u16 iiplh; |
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u16 iiplt; |
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u16 ioflh; |
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u16 ioflt; |
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u16 ioplh; |
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u16 ioplt; |
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u32 iidc; |
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u32 ictl; |
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u32 ifcpp; |
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u8 pad5[0x4]; |
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u16 mfac0; |
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u16 mfac1; |
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u16 mfac2; |
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u16 mfac3; |
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u16 mfac4; |
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u16 mfac5; |
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u16 mfac6; |
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u16 mfac7; |
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u16 ifcfh; |
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u16 ifcht; |
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u8 pad6[0x4]; |
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u32 iifmc; |
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u32 iodb; |
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u32 iodbc; |
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u32 ifbal; |
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u32 ifbah; |
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u32 ifsiz; |
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u32 ispd0; |
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u32 ispd1; |
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u32 ispd2; |
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u32 ispd3; |
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u32 ihipl; |
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u32 ihiph; |
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u32 ihopl; |
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u32 ihoph; |
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u32 iiipl; |
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u32 iiiph; |
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u32 iiopl; |
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u32 iioph; |
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u32 ifcpl; |
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u32 ifcph; |
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u8 pad7[0x8]; |
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u32 iopt; |
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}; |
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#endif /* _PPC440SPE_DMA_H */
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