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278 lines
6.6 KiB
278 lines
6.6 KiB
/* |
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* Driver for ICPlus PHYs |
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* |
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* Copyright (c) 2007 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/string.h> |
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#include <linux/errno.h> |
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#include <linux/unistd.h> |
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#include <linux/interrupt.h> |
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#include <linux/init.h> |
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#include <linux/delay.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/skbuff.h> |
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#include <linux/spinlock.h> |
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#include <linux/mm.h> |
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#include <linux/module.h> |
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#include <linux/mii.h> |
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#include <linux/ethtool.h> |
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#include <linux/phy.h> |
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#include <asm/io.h> |
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#include <asm/irq.h> |
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#include <asm/uaccess.h> |
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MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers"); |
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MODULE_AUTHOR("Michael Barkowski"); |
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MODULE_LICENSE("GPL"); |
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/* IP101A/G - IP1001 */ |
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#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ |
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#define IP1001_RXPHASE_SEL (1<<0) /* Add delay on RX_CLK */ |
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#define IP1001_TXPHASE_SEL (1<<1) /* Add delay on TX_CLK */ |
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#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ |
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#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ |
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#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ |
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#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ |
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#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */ |
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#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED |
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static int ip175c_config_init(struct phy_device *phydev) |
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{ |
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int err, i; |
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static int full_reset_performed; |
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if (full_reset_performed == 0) { |
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/* master reset */ |
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err = mdiobus_write(phydev->bus, 30, 0, 0x175c); |
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if (err < 0) |
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return err; |
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/* ensure no bus delays overlap reset period */ |
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err = mdiobus_read(phydev->bus, 30, 0); |
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/* data sheet specifies reset period is 2 msec */ |
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mdelay(2); |
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/* enable IP175C mode */ |
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err = mdiobus_write(phydev->bus, 29, 31, 0x175c); |
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if (err < 0) |
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return err; |
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/* Set MII0 speed and duplex (in PHY mode) */ |
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err = mdiobus_write(phydev->bus, 29, 22, 0x420); |
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if (err < 0) |
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return err; |
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/* reset switch ports */ |
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for (i = 0; i < 5; i++) { |
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err = mdiobus_write(phydev->bus, i, |
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MII_BMCR, BMCR_RESET); |
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if (err < 0) |
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return err; |
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} |
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for (i = 0; i < 5; i++) |
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err = mdiobus_read(phydev->bus, i, MII_BMCR); |
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mdelay(2); |
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full_reset_performed = 1; |
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} |
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if (phydev->addr != 4) { |
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phydev->state = PHY_RUNNING; |
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phydev->speed = SPEED_100; |
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phydev->duplex = DUPLEX_FULL; |
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phydev->link = 1; |
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netif_carrier_on(phydev->attached_dev); |
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} |
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return 0; |
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} |
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static int ip1xx_reset(struct phy_device *phydev) |
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{ |
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int bmcr; |
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/* Software Reset PHY */ |
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bmcr = phy_read(phydev, MII_BMCR); |
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if (bmcr < 0) |
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return bmcr; |
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bmcr |= BMCR_RESET; |
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bmcr = phy_write(phydev, MII_BMCR, bmcr); |
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if (bmcr < 0) |
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return bmcr; |
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do { |
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bmcr = phy_read(phydev, MII_BMCR); |
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if (bmcr < 0) |
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return bmcr; |
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} while (bmcr & BMCR_RESET); |
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return 0; |
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} |
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static int ip1001_config_init(struct phy_device *phydev) |
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{ |
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int c; |
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c = ip1xx_reset(phydev); |
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if (c < 0) |
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return c; |
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/* Enable Auto Power Saving mode */ |
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c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2); |
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if (c < 0) |
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return c; |
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c |= IP1001_APS_ON; |
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c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c); |
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if (c < 0) |
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return c; |
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || |
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || |
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || |
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { |
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c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); |
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if (c < 0) |
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return c; |
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c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL); |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
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c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL); |
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
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c |= IP1001_RXPHASE_SEL; |
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) |
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c |= IP1001_TXPHASE_SEL; |
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c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); |
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if (c < 0) |
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return c; |
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} |
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return 0; |
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} |
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static int ip101a_g_config_init(struct phy_device *phydev) |
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{ |
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int c; |
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c = ip1xx_reset(phydev); |
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if (c < 0) |
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return c; |
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/* INTR pin used: speed/link/duplex will cause an interrupt */ |
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c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT); |
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if (c < 0) |
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return c; |
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/* Enable Auto Power Saving mode */ |
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c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); |
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c |= IP101A_G_APS_ON; |
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return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); |
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} |
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static int ip175c_read_status(struct phy_device *phydev) |
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{ |
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if (phydev->addr == 4) /* WAN port */ |
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genphy_read_status(phydev); |
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else |
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/* Don't need to read status for switch ports */ |
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phydev->irq = PHY_IGNORE_INTERRUPT; |
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return 0; |
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} |
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static int ip175c_config_aneg(struct phy_device *phydev) |
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{ |
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if (phydev->addr == 4) /* WAN port */ |
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genphy_config_aneg(phydev); |
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return 0; |
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} |
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static int ip101a_g_ack_interrupt(struct phy_device *phydev) |
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{ |
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int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); |
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if (err < 0) |
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return err; |
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return 0; |
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} |
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static struct phy_driver icplus_driver[] = { |
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{ |
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.phy_id = 0x02430d80, |
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.name = "ICPlus IP175C", |
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.phy_id_mask = 0x0ffffff0, |
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.features = PHY_BASIC_FEATURES, |
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.config_init = &ip175c_config_init, |
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.config_aneg = &ip175c_config_aneg, |
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.read_status = &ip175c_read_status, |
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.suspend = genphy_suspend, |
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.resume = genphy_resume, |
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.driver = { .owner = THIS_MODULE,}, |
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}, { |
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.phy_id = 0x02430d90, |
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.name = "ICPlus IP1001", |
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.phy_id_mask = 0x0ffffff0, |
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.features = PHY_GBIT_FEATURES | SUPPORTED_Pause | |
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SUPPORTED_Asym_Pause, |
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.config_init = &ip1001_config_init, |
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.config_aneg = &genphy_config_aneg, |
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.read_status = &genphy_read_status, |
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.suspend = genphy_suspend, |
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.resume = genphy_resume, |
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.driver = { .owner = THIS_MODULE,}, |
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}, { |
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.phy_id = 0x02430c54, |
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.name = "ICPlus IP101A/G", |
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.phy_id_mask = 0x0ffffff0, |
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.features = PHY_BASIC_FEATURES | SUPPORTED_Pause | |
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SUPPORTED_Asym_Pause, |
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.flags = PHY_HAS_INTERRUPT, |
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.ack_interrupt = ip101a_g_ack_interrupt, |
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.config_init = &ip101a_g_config_init, |
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.config_aneg = &genphy_config_aneg, |
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.read_status = &genphy_read_status, |
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.suspend = genphy_suspend, |
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.resume = genphy_resume, |
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.driver = { .owner = THIS_MODULE,}, |
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} }; |
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static int __init icplus_init(void) |
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{ |
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return phy_drivers_register(icplus_driver, |
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ARRAY_SIZE(icplus_driver)); |
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} |
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static void __exit icplus_exit(void) |
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{ |
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phy_drivers_unregister(icplus_driver, |
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ARRAY_SIZE(icplus_driver)); |
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} |
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module_init(icplus_init); |
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module_exit(icplus_exit); |
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static struct mdio_device_id __maybe_unused icplus_tbl[] = { |
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{ 0x02430d80, 0x0ffffff0 }, |
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{ 0x02430d90, 0x0ffffff0 }, |
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{ 0x02430c54, 0x0ffffff0 }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(mdio, icplus_tbl);
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