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430 lines
11 KiB
430 lines
11 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org) |
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
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*/ |
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#ifndef _ASM_SPINLOCK_H |
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#define _ASM_SPINLOCK_H |
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#include <linux/compiler.h> |
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#include <asm/barrier.h> |
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#include <asm/compiler.h> |
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#include <asm/war.h> |
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/* |
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* Your basic SMP spinlocks, allowing only a single CPU anywhere |
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* |
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* Simple spin lock operations. There are two variants, one clears IRQ's |
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* on the local processor, one does not. |
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* |
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* These are fair FIFO ticket locks |
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* |
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* (the type definitions are in asm/spinlock_types.h) |
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*/ |
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/* |
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* Ticket locks are conceptually two parts, one indicating the current head of |
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* the queue, and the other indicating the current tail. The lock is acquired |
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* by atomically noting the tail and incrementing it by one (thus adding |
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* ourself to the queue and noting our position), then waiting until the head |
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* becomes equal to the the initial value of the tail. |
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*/ |
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static inline int arch_spin_is_locked(arch_spinlock_t *lock) |
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{ |
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u32 counters = ACCESS_ONCE(lock->lock); |
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return ((counters >> 16) ^ counters) & 0xffff; |
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} |
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock) |
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{ |
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return lock.h.serving_now == lock.h.ticket; |
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} |
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) |
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#define arch_spin_unlock_wait(x) \ |
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while (arch_spin_is_locked(x)) { cpu_relax(); } |
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static inline int arch_spin_is_contended(arch_spinlock_t *lock) |
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{ |
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u32 counters = ACCESS_ONCE(lock->lock); |
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return (((counters >> 16) - counters) & 0xffff) > 1; |
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} |
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#define arch_spin_is_contended arch_spin_is_contended |
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static inline void arch_spin_lock(arch_spinlock_t *lock) |
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{ |
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int my_ticket; |
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int tmp; |
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int inc = 0x10000; |
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if (R10000_LLSC_WAR) { |
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__asm__ __volatile__ ( |
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" .set push # arch_spin_lock \n" |
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" .set noreorder \n" |
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" \n" |
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"1: ll %[ticket], %[ticket_ptr] \n" |
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" addu %[my_ticket], %[ticket], %[inc] \n" |
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" sc %[my_ticket], %[ticket_ptr] \n" |
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" beqzl %[my_ticket], 1b \n" |
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" nop \n" |
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" srl %[my_ticket], %[ticket], 16 \n" |
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" andi %[ticket], %[ticket], 0xffff \n" |
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" bne %[ticket], %[my_ticket], 4f \n" |
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" subu %[ticket], %[my_ticket], %[ticket] \n" |
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"2: \n" |
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" .subsection 2 \n" |
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"4: andi %[ticket], %[ticket], 0xffff \n" |
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" sll %[ticket], 5 \n" |
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" \n" |
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"6: bnez %[ticket], 6b \n" |
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" subu %[ticket], 1 \n" |
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" \n" |
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" lhu %[ticket], %[serving_now_ptr] \n" |
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" beq %[ticket], %[my_ticket], 2b \n" |
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" subu %[ticket], %[my_ticket], %[ticket] \n" |
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" b 4b \n" |
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" subu %[ticket], %[ticket], 1 \n" |
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" .previous \n" |
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" .set pop \n" |
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: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock), |
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[serving_now_ptr] "+m" (lock->h.serving_now), |
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[ticket] "=&r" (tmp), |
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[my_ticket] "=&r" (my_ticket) |
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: [inc] "r" (inc)); |
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} else { |
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__asm__ __volatile__ ( |
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" .set push # arch_spin_lock \n" |
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" .set noreorder \n" |
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" \n" |
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"1: ll %[ticket], %[ticket_ptr] \n" |
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" addu %[my_ticket], %[ticket], %[inc] \n" |
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" sc %[my_ticket], %[ticket_ptr] \n" |
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" beqz %[my_ticket], 1b \n" |
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" srl %[my_ticket], %[ticket], 16 \n" |
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" andi %[ticket], %[ticket], 0xffff \n" |
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" bne %[ticket], %[my_ticket], 4f \n" |
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" subu %[ticket], %[my_ticket], %[ticket] \n" |
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"2: .insn \n" |
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" .subsection 2 \n" |
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"4: andi %[ticket], %[ticket], 0xffff \n" |
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" sll %[ticket], 5 \n" |
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" \n" |
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"6: bnez %[ticket], 6b \n" |
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" subu %[ticket], 1 \n" |
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" \n" |
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" lhu %[ticket], %[serving_now_ptr] \n" |
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" beq %[ticket], %[my_ticket], 2b \n" |
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" subu %[ticket], %[my_ticket], %[ticket] \n" |
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" b 4b \n" |
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" subu %[ticket], %[ticket], 1 \n" |
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" .previous \n" |
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" .set pop \n" |
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: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock), |
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[serving_now_ptr] "+m" (lock->h.serving_now), |
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[ticket] "=&r" (tmp), |
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[my_ticket] "=&r" (my_ticket) |
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: [inc] "r" (inc)); |
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} |
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smp_llsc_mb(); |
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} |
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static inline void arch_spin_unlock(arch_spinlock_t *lock) |
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{ |
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unsigned int serving_now = lock->h.serving_now + 1; |
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wmb(); |
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lock->h.serving_now = (u16)serving_now; |
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nudge_writes(); |
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} |
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static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) |
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{ |
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int tmp, tmp2, tmp3; |
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int inc = 0x10000; |
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if (R10000_LLSC_WAR) { |
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__asm__ __volatile__ ( |
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" .set push # arch_spin_trylock \n" |
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" .set noreorder \n" |
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" \n" |
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"1: ll %[ticket], %[ticket_ptr] \n" |
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" srl %[my_ticket], %[ticket], 16 \n" |
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" andi %[now_serving], %[ticket], 0xffff \n" |
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" bne %[my_ticket], %[now_serving], 3f \n" |
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" addu %[ticket], %[ticket], %[inc] \n" |
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" sc %[ticket], %[ticket_ptr] \n" |
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" beqzl %[ticket], 1b \n" |
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" li %[ticket], 1 \n" |
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"2: \n" |
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" .subsection 2 \n" |
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"3: b 2b \n" |
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" li %[ticket], 0 \n" |
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" .previous \n" |
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" .set pop \n" |
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: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock), |
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[ticket] "=&r" (tmp), |
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[my_ticket] "=&r" (tmp2), |
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[now_serving] "=&r" (tmp3) |
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: [inc] "r" (inc)); |
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} else { |
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__asm__ __volatile__ ( |
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" .set push # arch_spin_trylock \n" |
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" .set noreorder \n" |
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" \n" |
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"1: ll %[ticket], %[ticket_ptr] \n" |
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" srl %[my_ticket], %[ticket], 16 \n" |
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" andi %[now_serving], %[ticket], 0xffff \n" |
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" bne %[my_ticket], %[now_serving], 3f \n" |
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" addu %[ticket], %[ticket], %[inc] \n" |
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" sc %[ticket], %[ticket_ptr] \n" |
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" beqz %[ticket], 1b \n" |
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" li %[ticket], 1 \n" |
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"2: .insn \n" |
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" .subsection 2 \n" |
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"3: b 2b \n" |
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" li %[ticket], 0 \n" |
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" .previous \n" |
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" .set pop \n" |
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: [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock), |
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[ticket] "=&r" (tmp), |
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[my_ticket] "=&r" (tmp2), |
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[now_serving] "=&r" (tmp3) |
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: [inc] "r" (inc)); |
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} |
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smp_llsc_mb(); |
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return tmp; |
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} |
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/* |
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* Read-write spinlocks, allowing multiple readers but only one writer. |
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* |
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* NOTE! it is quite common to have readers in interrupts but no interrupt |
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* writers. For those circumstances we can "mix" irq-safe locks - any writer |
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* needs to get a irq-safe write-lock, but readers can get non-irqsafe |
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* read-locks. |
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*/ |
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/* |
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* read_can_lock - would read_trylock() succeed? |
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* @lock: the rwlock in question. |
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*/ |
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#define arch_read_can_lock(rw) ((rw)->lock >= 0) |
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/* |
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* write_can_lock - would write_trylock() succeed? |
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* @lock: the rwlock in question. |
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*/ |
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#define arch_write_can_lock(rw) (!(rw)->lock) |
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static inline void arch_read_lock(arch_rwlock_t *rw) |
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{ |
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unsigned int tmp; |
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if (R10000_LLSC_WAR) { |
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__asm__ __volatile__( |
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" .set noreorder # arch_read_lock \n" |
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"1: ll %1, %2 \n" |
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" bltz %1, 1b \n" |
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" addu %1, 1 \n" |
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" sc %1, %0 \n" |
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" beqzl %1, 1b \n" |
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" nop \n" |
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" .set reorder \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} else { |
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do { |
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__asm__ __volatile__( |
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"1: ll %1, %2 # arch_read_lock \n" |
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" bltz %1, 1b \n" |
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" addu %1, 1 \n" |
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"2: sc %1, %0 \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} while (unlikely(!tmp)); |
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} |
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smp_llsc_mb(); |
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} |
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static inline void arch_read_unlock(arch_rwlock_t *rw) |
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{ |
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unsigned int tmp; |
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smp_mb__before_llsc(); |
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if (R10000_LLSC_WAR) { |
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__asm__ __volatile__( |
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"1: ll %1, %2 # arch_read_unlock \n" |
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" addiu %1, -1 \n" |
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" sc %1, %0 \n" |
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" beqzl %1, 1b \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} else { |
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do { |
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__asm__ __volatile__( |
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"1: ll %1, %2 # arch_read_unlock \n" |
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" addiu %1, -1 \n" |
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" sc %1, %0 \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} while (unlikely(!tmp)); |
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} |
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} |
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static inline void arch_write_lock(arch_rwlock_t *rw) |
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{ |
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unsigned int tmp; |
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if (R10000_LLSC_WAR) { |
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__asm__ __volatile__( |
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" .set noreorder # arch_write_lock \n" |
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"1: ll %1, %2 \n" |
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" bnez %1, 1b \n" |
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" lui %1, 0x8000 \n" |
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" sc %1, %0 \n" |
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" beqzl %1, 1b \n" |
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" nop \n" |
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" .set reorder \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} else { |
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do { |
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__asm__ __volatile__( |
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"1: ll %1, %2 # arch_write_lock \n" |
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" bnez %1, 1b \n" |
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" lui %1, 0x8000 \n" |
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"2: sc %1, %0 \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} while (unlikely(!tmp)); |
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} |
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smp_llsc_mb(); |
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} |
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static inline void arch_write_unlock(arch_rwlock_t *rw) |
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{ |
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smp_mb__before_llsc(); |
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__asm__ __volatile__( |
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" # arch_write_unlock \n" |
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" sw $0, %0 \n" |
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: "=m" (rw->lock) |
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: "m" (rw->lock) |
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: "memory"); |
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} |
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static inline int arch_read_trylock(arch_rwlock_t *rw) |
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{ |
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unsigned int tmp; |
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int ret; |
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if (R10000_LLSC_WAR) { |
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__asm__ __volatile__( |
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" .set noreorder # arch_read_trylock \n" |
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" li %2, 0 \n" |
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"1: ll %1, %3 \n" |
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" bltz %1, 2f \n" |
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" addu %1, 1 \n" |
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" sc %1, %0 \n" |
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" .set reorder \n" |
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" beqzl %1, 1b \n" |
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" nop \n" |
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__WEAK_LLSC_MB |
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" li %2, 1 \n" |
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"2: \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} else { |
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__asm__ __volatile__( |
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" .set noreorder # arch_read_trylock \n" |
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" li %2, 0 \n" |
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"1: ll %1, %3 \n" |
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" bltz %1, 2f \n" |
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" addu %1, 1 \n" |
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" sc %1, %0 \n" |
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" beqz %1, 1b \n" |
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" nop \n" |
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" .set reorder \n" |
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__WEAK_LLSC_MB |
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" li %2, 1 \n" |
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"2: .insn \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} |
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return ret; |
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} |
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static inline int arch_write_trylock(arch_rwlock_t *rw) |
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{ |
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unsigned int tmp; |
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int ret; |
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if (R10000_LLSC_WAR) { |
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__asm__ __volatile__( |
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" .set noreorder # arch_write_trylock \n" |
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" li %2, 0 \n" |
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"1: ll %1, %3 \n" |
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" bnez %1, 2f \n" |
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" lui %1, 0x8000 \n" |
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" sc %1, %0 \n" |
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" beqzl %1, 1b \n" |
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" nop \n" |
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__WEAK_LLSC_MB |
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" li %2, 1 \n" |
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" .set reorder \n" |
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"2: \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} else { |
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do { |
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__asm__ __volatile__( |
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" ll %1, %3 # arch_write_trylock \n" |
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" li %2, 0 \n" |
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" bnez %1, 2f \n" |
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" lui %1, 0x8000 \n" |
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" sc %1, %0 \n" |
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" li %2, 1 \n" |
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"2: .insn \n" |
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: "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), |
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"=&r" (ret) |
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: GCC_OFF_SMALL_ASM() (rw->lock) |
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: "memory"); |
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} while (unlikely(!tmp)); |
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smp_llsc_mb(); |
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} |
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return ret; |
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} |
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) |
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) |
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#define arch_spin_relax(lock) cpu_relax() |
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#define arch_read_relax(lock) cpu_relax() |
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#define arch_write_relax(lock) cpu_relax() |
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#endif /* _ASM_SPINLOCK_H */
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