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90 lines
2.1 KiB
90 lines
2.1 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2007 by Ralf Baechle |
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*/ |
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#include <linux/clocksource.h> |
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#include <linux/init.h> |
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#include <linux/sched_clock.h> |
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#include <asm/time.h> |
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static cycle_t c0_hpt_read(struct clocksource *cs) |
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{ |
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return read_c0_count(); |
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} |
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static struct clocksource clocksource_mips = { |
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.name = "MIPS", |
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.read = c0_hpt_read, |
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.mask = CLOCKSOURCE_MASK(32), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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static u64 __maybe_unused notrace r4k_read_sched_clock(void) |
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{ |
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return read_c0_count(); |
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} |
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static inline unsigned int rdhwr_count(void) |
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{ |
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unsigned int count; |
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__asm__ __volatile__( |
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" .set push\n" |
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" .set mips32r2\n" |
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" rdhwr %0, $2\n" |
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" .set pop\n" |
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: "=r" (count)); |
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return count; |
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} |
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static bool rdhwr_count_usable(void) |
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{ |
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unsigned int prev, curr, i; |
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/* |
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* Older QEMUs have a broken implementation of RDHWR for the CP0 count |
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* which always returns a constant value. Try to identify this and don't |
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* use it in the VDSO if it is broken. This workaround can be removed |
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* once the fix has been in QEMU stable for a reasonable amount of time. |
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*/ |
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for (i = 0, prev = rdhwr_count(); i < 100; i++) { |
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curr = rdhwr_count(); |
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if (curr != prev) |
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return true; |
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prev = curr; |
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} |
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pr_warn("Not using R4K clocksource in VDSO due to broken RDHWR\n"); |
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return false; |
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} |
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int __init init_r4k_clocksource(void) |
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{ |
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if (!cpu_has_counter || !mips_hpt_frequency) |
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return -ENXIO; |
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/* Calculate a somewhat reasonable rating value */ |
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clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; |
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/* |
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* R2 onwards makes the count accessible to user mode so it can be used |
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* by the VDSO (HWREna is configured by configure_hwrena()). |
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*/ |
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if (cpu_has_mips_r2_r6 && rdhwr_count_usable()) |
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clocksource_mips.archdata.vdso_clock_mode = VDSO_CLOCK_R4K; |
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clocksource_register_hz(&clocksource_mips, mips_hpt_frequency); |
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#ifndef CONFIG_CPU_FREQ |
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sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency); |
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#endif |
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return 0; |
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}
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