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121 lines
2.6 KiB
121 lines
2.6 KiB
#ifndef _ASM_X86_AMD_NB_H |
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#define _ASM_X86_AMD_NB_H |
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#include <linux/ioport.h> |
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#include <linux/pci.h> |
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struct amd_nb_bus_dev_range { |
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u8 bus; |
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u8 dev_base; |
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u8 dev_limit; |
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}; |
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extern const struct pci_device_id amd_nb_misc_ids[]; |
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extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; |
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extern bool early_is_amd_nb(u32 value); |
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extern struct resource *amd_get_mmconfig_range(struct resource *res); |
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extern int amd_cache_northbridges(void); |
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extern void amd_flush_garts(void); |
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extern int amd_numa_init(void); |
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extern int amd_get_subcaches(int); |
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extern int amd_set_subcaches(int, unsigned long); |
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struct amd_l3_cache { |
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unsigned indices; |
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u8 subcaches[4]; |
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}; |
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struct threshold_block { |
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unsigned int block; |
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unsigned int bank; |
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unsigned int cpu; |
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u32 address; |
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u16 interrupt_enable; |
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bool interrupt_capable; |
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u16 threshold_limit; |
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struct kobject kobj; |
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struct list_head miscj; |
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}; |
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struct threshold_bank { |
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struct kobject *kobj; |
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struct threshold_block *blocks; |
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/* initialized to the number of CPUs on the node sharing this bank */ |
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atomic_t cpus; |
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}; |
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struct amd_northbridge { |
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struct pci_dev *misc; |
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struct pci_dev *link; |
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struct amd_l3_cache l3_cache; |
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struct threshold_bank *bank4; |
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}; |
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struct amd_northbridge_info { |
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u16 num; |
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u64 flags; |
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struct amd_northbridge *nb; |
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}; |
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extern struct amd_northbridge_info amd_northbridges; |
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#define AMD_NB_GART BIT(0) |
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#define AMD_NB_L3_INDEX_DISABLE BIT(1) |
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#define AMD_NB_L3_PARTITIONING BIT(2) |
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#ifdef CONFIG_AMD_NB |
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static inline u16 amd_nb_num(void) |
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{ |
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return amd_northbridges.num; |
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} |
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static inline bool amd_nb_has_feature(unsigned feature) |
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{ |
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return ((amd_northbridges.flags & feature) == feature); |
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} |
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static inline struct amd_northbridge *node_to_amd_nb(int node) |
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{ |
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return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL; |
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} |
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static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) |
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{ |
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struct pci_dev *misc; |
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int i; |
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for (i = 0; i != amd_nb_num(); i++) { |
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misc = node_to_amd_nb(i)->misc; |
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if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) && |
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PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn)) |
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return i; |
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} |
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WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev)); |
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return 0; |
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} |
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static inline bool amd_gart_present(void) |
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{ |
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/* GART present only on Fam15h, upto model 0fh */ |
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || |
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(boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) |
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return true; |
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return false; |
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} |
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#else |
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#define amd_nb_num(x) 0 |
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#define amd_nb_has_feature(x) false |
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#define node_to_amd_nb(x) NULL |
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#define amd_gart_present(x) false |
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#endif |
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#endif /* _ASM_X86_AMD_NB_H */
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