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430 lines
11 KiB
430 lines
11 KiB
/****************************************************************************** |
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* |
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* Copyright (C) 2009-2012 Broadcom Corporation |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); |
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* you may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at: |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0 |
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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* |
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******************************************************************************/ |
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/****************************************************************************** |
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* |
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* Filename: bt_vendor_brcm.h |
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* |
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* Description: A wrapper header file of bt_vendor_lib.h |
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* |
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* Contains definitions specific for interfacing with Broadcom |
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* Bluetooth chipsets |
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* |
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******************************************************************************/ |
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#ifndef BT_VENDOR_BRCM_H |
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#define BT_VENDOR_BRCM_H |
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#include "bt_vendor_lib.h" |
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#include "vnd_buildcfg.h" |
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/****************************************************************************** |
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** Constants & Macros |
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******************************************************************************/ |
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#ifndef FALSE |
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#define FALSE 0 |
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#endif |
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#ifndef TRUE |
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#define TRUE (!FALSE) |
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#endif |
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#ifndef VENDOR_LIB_RUNTIME_TUNING_ENABLED |
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#define VENDOR_LIB_RUNTIME_TUNING_ENABLED FALSE |
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#endif |
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/* Run-time configuration file */ |
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#ifndef VENDOR_LIB_CONF_FILE |
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#define VENDOR_LIB_CONF_FILE "/etc/bluetooth/bt_vendor.conf" |
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#endif |
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/* Device port name where Bluetooth controller attached */ |
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#ifndef BLUETOOTH_UART_DEVICE_PORT |
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#define BLUETOOTH_UART_DEVICE_PORT "/dev/ttyO1" /* maguro */ |
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#endif |
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/* Location of firmware patch files */ |
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#ifndef FW_PATCHFILE_LOCATION |
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#define FW_PATCHFILE_LOCATION "/vendor/firmware/" /* maguro */ |
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#endif |
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#ifndef UART_TARGET_BAUD_RATE |
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#define UART_TARGET_BAUD_RATE 3000000 |
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#endif |
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/* The millisecond delay pauses on HCI transport after firmware patches |
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* were downloaded. This gives some time for firmware to restart with |
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* patches before host attempts to send down any HCI commands. |
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* |
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* Note: It has been discovered that BCM43241B0 needs at least 200ms |
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* settlement delay in here. Without the delay, a Hardware Error event |
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* from BCM43241B0 had been seen in HCI upstream path right after the |
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* host sent the HCI_VSC_SET_BDADDR commad to the controller at higher |
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* baud. |
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*/ |
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#ifndef FW_PATCH_SETTLEMENT_DELAY_MS |
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#define FW_PATCH_SETTLEMENT_DELAY_MS 0 |
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#endif |
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/* The Bluetooth Device Aaddress source switch: |
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* |
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* -FALSE- (default value) |
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* Get the factory BDADDR from device's file system. Normally the BDADDR is |
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* stored in the location pointed by the PROPERTY_BT_BDADDR_PATH (defined in |
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* btif_common.h file) property. |
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* |
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* -TRUE- |
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* If the Bluetooth Controller has equipped with a non-volatile memory (such |
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* as BCM4330's OTP memory), the factory BDADDR can be stored in there and |
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* retrieved by the stack while enabling BT. |
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* !!! WARNING !!! Make sure that the OTP feature has been enabled in the |
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* firmware patchram (.hcd) file. |
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*/ |
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#ifndef USE_CONTROLLER_BDADDR |
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#define USE_CONTROLLER_BDADDR FALSE |
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#endif |
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/* sleep mode |
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0: disable |
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1: UART with Host wake/BT wake out of band signals |
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*/ |
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#ifndef LPM_SLEEP_MODE |
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#define LPM_SLEEP_MODE 1 |
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#endif |
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/* Host Stack Idle Threshold in 300ms or 25ms |
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In sleep mode 1, this is the number of firmware loops executed with no |
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activity before the Host wake line is deasserted. Activity includes HCI |
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traffic excluding certain sleep mode commands and the presence of SCO |
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connections if the "Allow Host Sleep During SCO" flag is not set to 1. |
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Each count of this parameter is roughly equivalent to 300ms or 25ms. |
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*/ |
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#ifndef LPM_IDLE_THRESHOLD |
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#define LPM_IDLE_THRESHOLD 1 |
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#endif |
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/* Host Controller Idle Threshold in 300ms or 25ms |
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This is the number of firmware loops executed with no activity before the |
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HC is considered idle. Depending on the mode, HC may then attempt to sleep. |
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Activity includes HCI traffic excluding certain sleep mode commands and |
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the presence of ACL/SCO connections. |
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*/ |
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#ifndef LPM_HC_IDLE_THRESHOLD |
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#define LPM_HC_IDLE_THRESHOLD 1 |
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#endif |
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/* BT_WAKE Polarity - 0=Active Low, 1= Active High */ |
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#ifndef LPM_BT_WAKE_POLARITY |
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#define LPM_BT_WAKE_POLARITY 1 /* maguro */ |
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#endif |
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/* HOST_WAKE Polarity - 0=Active Low, 1= Active High */ |
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#ifndef LPM_HOST_WAKE_POLARITY |
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#define LPM_HOST_WAKE_POLARITY 1 /* maguro */ |
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#endif |
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/* LPM_ALLOW_HOST_SLEEP_DURING_SCO |
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When this flag is set to 0, the host is not allowed to sleep while |
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an SCO is active. In sleep mode 1, the device will keep the host |
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wake line asserted while an SCO is active. |
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When this flag is set to 1, the host can sleep while an SCO is active. |
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This flag should only be set to 1 if SCO traffic is directed to the PCM |
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interface. |
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*/ |
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#ifndef LPM_ALLOW_HOST_SLEEP_DURING_SCO |
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#define LPM_ALLOW_HOST_SLEEP_DURING_SCO 1 |
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#endif |
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/* LPM_COMBINE_SLEEP_MODE_AND_LPM |
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In Mode 0, always set byte 7 to 0. In sleep mode 1, device always |
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requires permission to sleep between scans / periodic inquiries regardless |
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of the setting of this byte. In sleep mode 1, if byte is set, device must |
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have "permission" to sleep during the low power modes of sniff, hold, and |
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park. If byte is not set, device can sleep without permission during these |
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modes. Permission to sleep in Mode 1 is obtained if the BT_WAKE signal is |
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not asserted. |
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*/ |
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#ifndef LPM_COMBINE_SLEEP_MODE_AND_LPM |
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#define LPM_COMBINE_SLEEP_MODE_AND_LPM 1 |
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#endif |
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/* LPM_ENABLE_UART_TXD_TRI_STATE |
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When set to 0, the device will not tristate its UART TX line before going |
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to sleep. |
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When set to 1, the device will tristate its UART TX line before going to |
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sleep. |
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*/ |
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#ifndef LPM_ENABLE_UART_TXD_TRI_STATE |
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#define LPM_ENABLE_UART_TXD_TRI_STATE 0 |
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#endif |
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/* LPM_PULSED_HOST_WAKE |
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*/ |
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#ifndef LPM_PULSED_HOST_WAKE |
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#define LPM_PULSED_HOST_WAKE 0 |
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#endif |
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/* LPM_IDLE_TIMEOUT_MULTIPLE |
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The multiple factor of host stack idle threshold in 300ms/25ms |
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*/ |
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#ifndef LPM_IDLE_TIMEOUT_MULTIPLE |
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#define LPM_IDLE_TIMEOUT_MULTIPLE 10 |
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#endif |
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/* BT_WAKE_VIA_USERIAL_IOCTL |
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Use userial ioctl function to control BT_WAKE signal |
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*/ |
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#ifndef BT_WAKE_VIA_USERIAL_IOCTL |
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#define BT_WAKE_VIA_USERIAL_IOCTL FALSE |
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#endif |
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/* BT_WAKE_USERIAL_LDISC |
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Use line discipline if the BT_WAKE control is in line discipline |
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*/ |
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#ifndef BT_WAKE_USERIAL_LDISC |
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#define BT_WAKE_USERIAL_LDISC FALSE |
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#endif |
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/* BT_WAKE_VIA_PROC |
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LPM & BT_WAKE control through PROC nodes |
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*/ |
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#ifndef BT_WAKE_VIA_PROC |
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#define BT_WAKE_VIA_PROC FALSE |
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#endif |
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#ifndef BT_WAKE_VIA_PROC_NOTIFY_DEASSERT |
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#define BT_WAKE_VIA_PROC_NOTIFY_DEASSERT FALSE |
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#endif |
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/* N_BRCM_HCI |
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UART ioctl line discipline |
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*/ |
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#ifndef N_BRCM_HCI |
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#define N_BRCM_HCI 25 |
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#endif |
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/* SCO_CFG_INCLUDED |
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Do SCO configuration by default. If the firmware patch had been embedded |
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with desired SCO configuration, set this FALSE to bypass configuration |
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from host software. |
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*/ |
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#ifndef SCO_CFG_INCLUDED |
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#define SCO_CFG_INCLUDED TRUE |
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#endif |
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#ifndef SCO_USE_I2S_INTERFACE |
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#define SCO_USE_I2S_INTERFACE FALSE |
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#endif |
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#define SCO_I2SPCM_PARAM_SIZE 4 |
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/* SCO_WBS_SAMPLE_RATE |
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0 : 8K |
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1 : 16K |
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2 : 4K |
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This macro is used for setting WBS sampling rate for a SCO connection |
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If the mobile network supports WBS, we need to use 16KHz as default |
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but if the platform doesn't support 16KHz, the sample rate can be |
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overriden to 8KHz by setting this to 0. |
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*/ |
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#ifndef SCO_WBS_SAMPLE_RATE |
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#define SCO_WBS_SAMPLE_RATE 1 |
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#endif |
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/* SCO_I2SPCM_IF_MODE - 0=Disable, 1=Enable */ |
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#ifndef SCO_I2SPCM_IF_MODE |
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#define SCO_I2SPCM_IF_MODE 1 |
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#endif |
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/* SCO_I2SPCM_IF_ROLE - 0=Slave, 1=Master */ |
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#ifndef SCO_I2SPCM_IF_ROLE |
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#define SCO_I2SPCM_IF_ROLE 1 |
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#endif |
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/* SCO_I2SPCM_IF_SAMPLE_RATE |
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0 : 8K |
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1 : 16K |
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2 : 4K |
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*/ |
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#ifndef SCO_I2SPCM_IF_SAMPLE_RATE |
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#define SCO_I2SPCM_IF_SAMPLE_RATE 0 |
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#endif |
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/* SCO_I2SPCM_IF_CLOCK_RATE |
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0 : 128K |
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1 : 256K |
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2 : 512K |
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3 : 1024K |
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4 : 2048K |
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*/ |
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#ifndef SCO_I2SPCM_IF_CLOCK_RATE |
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#define SCO_I2SPCM_IF_CLOCK_RATE 1 |
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#endif |
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/* SCO_I2SPCM_IF_CLOCK_RATE4WBS |
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0 : 128K |
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1 : 256K |
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2 : 512K |
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3 : 1024K |
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4 : 2048K |
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*/ |
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#ifndef SCO_I2SPCM_IF_CLOCK_RATE4WBS |
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#define SCO_I2SPCM_IF_CLOCK_RATE4WBS 2 |
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#endif |
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#define SCO_PCM_PARAM_SIZE 5 |
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/* SCO_PCM_ROUTING |
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0 : PCM |
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1 : Transport |
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2 : Codec |
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3 : I2S |
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*/ |
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#ifndef SCO_PCM_ROUTING |
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#define SCO_PCM_ROUTING 0 |
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#endif |
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/* SCO_PCM_IF_CLOCK_RATE |
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NOTICE: suggested to be consistent with SCO_I2SPCM_IF_CLOCK_RATE |
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0 : 128K |
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1 : 256K |
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2 : 512K |
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3 : 1024K |
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4 : 2048K |
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*/ |
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#ifndef SCO_PCM_IF_CLOCK_RATE |
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#define SCO_PCM_IF_CLOCK_RATE 4 |
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#endif |
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/* SCO_PCM_IF_FRAME_TYPE - 0=Short, 1=Long */ |
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#ifndef SCO_PCM_IF_FRAME_TYPE |
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#define SCO_PCM_IF_FRAME_TYPE 0 |
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#endif |
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/* SCO_PCM_IF_SYNC_MODE |
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NOTICE: in most usage cases the value will be the same as |
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SCO_PCM_IF_CLOCK_MODE setting |
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0 : Slave |
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1 : Master |
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*/ |
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#ifndef SCO_PCM_IF_SYNC_MODE |
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#define SCO_PCM_IF_SYNC_MODE 0 |
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#endif |
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/* SCO_PCM_IF_CLOCK_MODE |
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NOTICE: suggested to be consistent with SCO_I2SPCM_IF_ROLE |
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0 : Slave |
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1 : Master |
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*/ |
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#ifndef SCO_PCM_IF_CLOCK_MODE |
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#define SCO_PCM_IF_CLOCK_MODE 0 |
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#endif |
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#define PCM_DATA_FORMAT_PARAM_SIZE 5 |
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/* PCM_DATA_FMT_SHIFT_MODE |
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0 : MSB first |
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1 : LSB first |
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*/ |
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#ifndef PCM_DATA_FMT_SHIFT_MODE |
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#define PCM_DATA_FMT_SHIFT_MODE 0 |
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#endif |
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/* PCM_DATA_FMT_FILL_BITS |
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Specifies the value with which to fill unused bits |
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if Fill_Method is set to programmable |
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*/ |
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#ifndef PCM_DATA_FMT_FILL_BITS |
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#define PCM_DATA_FMT_FILL_BITS 0 |
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#endif |
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/* PCM_DATA_FMT_FILL_METHOD |
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0 : 0's |
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1 : 1's |
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2 : Signed |
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3 : Programmable |
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*/ |
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#ifndef PCM_DATA_FMT_FILL_METHOD |
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#define PCM_DATA_FMT_FILL_METHOD 3 |
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#endif |
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/* PCM_DATA_FMT_FILL_NUM |
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Specifies the number of bits to be filled |
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*/ |
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#ifndef PCM_DATA_FMT_FILL_NUM |
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#define PCM_DATA_FMT_FILL_NUM 0 |
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#endif |
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/* PCM_DATA_FMT_JUSTIFY_MODE |
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0 : Left justify (fill data shifted out last) |
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1 : Right justify (fill data shifted out first) |
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*/ |
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#ifndef PCM_DATA_FMT_JUSTIFY_MODE |
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#define PCM_DATA_FMT_JUSTIFY_MODE 0 |
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#endif |
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/* HW_END_WITH_HCI_RESET |
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Sample code implementation of sending a HCI_RESET command during the epilog |
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process. It calls back to the callers after command complete of HCI_RESET |
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is received. |
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*/ |
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#ifndef HW_END_WITH_HCI_RESET |
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#define HW_END_WITH_HCI_RESET TRUE |
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#endif |
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/****************************************************************************** |
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** Extern variables and functions |
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******************************************************************************/ |
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extern bt_vendor_callbacks_t *bt_vendor_cbacks; |
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extern int hw_set_audio_state(bt_vendor_op_audio_state_t *p_state); |
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#endif /* BT_VENDOR_BRCM_H */ |
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