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/* |
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// Copyright (c) 2014 Intel Corporation |
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// |
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// Licensed under the Apache License, Version 2.0 (the "License"); |
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// you may not use this file except in compliance with the License. |
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// You may obtain a copy of the License at |
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// |
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// http://www.apache.org/licenses/LICENSE-2.0 |
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// |
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// Unless required by applicable law or agreed to in writing, software |
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// distributed under the License is distributed on an "AS IS" BASIS, |
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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// See the License for the specific language governing permissions and |
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// limitations under the License. |
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*/ |
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#ifndef OVERLAY_HARDWARE_H |
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#define OVERLAY_HARDWARE_H |
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namespace android { |
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namespace intel { |
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// only one overlay data buffer for testing |
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#define INTEL_OVERLAY_BUFFER_NUM 1 |
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#define INTEL_OVERLAY_MAX_WIDTH 2048 |
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#define INTEL_OVERLAY_MAX_HEIGHT 2048 |
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#define INTEL_OVERLAY_MIN_STRIDE 512 |
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#define INTEL_OVERLAY_MAX_STRIDE_PACKED (8 * 1024) |
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#define INTEL_OVERLAY_MAX_STRIDE_LINEAR (4 * 1024) |
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#define INTEL_OVERLAY_MAX_SCALING_RATIO 7 |
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// Polyphase filter coefficients |
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#define N_HORIZ_Y_TAPS 5 |
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#define N_VERT_Y_TAPS 3 |
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#define N_HORIZ_UV_TAPS 3 |
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#define N_VERT_UV_TAPS 3 |
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#define N_PHASES 17 |
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#define MAX_TAPS 5 |
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// Filter cutoff frequency limits. |
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#define MIN_CUTOFF_FREQ 1.0 |
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#define MAX_CUTOFF_FREQ 3.0 |
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// Overlay init micros |
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#define OVERLAY_INIT_CONTRAST 0x4b |
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#define OVERLAY_INIT_BRIGHTNESS -19 |
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#define OVERLAY_INIT_SATURATION 0x92 |
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#define OVERLAY_INIT_GAMMA0 0x080808 |
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#define OVERLAY_INIT_GAMMA1 0x101010 |
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#define OVERLAY_INIT_GAMMA2 0x202020 |
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#define OVERLAY_INIT_GAMMA3 0x404040 |
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#define OVERLAY_INIT_GAMMA4 0x808080 |
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#define OVERLAY_INIT_GAMMA5 0xc0c0c0 |
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#define OVERLAY_INIT_COLORKEY 0 |
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#define OVERLAY_INIT_COLORKEYMASK ((0x0 << 31) | (0X0 << 30)) |
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#define OVERLAY_INIT_CONFIG ((0x1 << 18) | (0x1 << 3)) |
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// overlay register values |
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#define OVERLAY_FORMAT_MASK (0xf << 10) |
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#define OVERLAY_FORMAT_PACKED_YUV422 (0x8 << 10) |
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#define OVERLAY_FORMAT_PLANAR_NV12_1 (0x7 << 10) |
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#define OVERLAY_FORMAT_PLANAR_NV12_2 (0xb << 10) |
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#define OVERLAY_FORMAT_PLANAR_YUV420 (0xc << 10) |
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#define OVERLAY_FORMAT_PLANAR_YUV422 (0xd << 10) |
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#define OVERLAY_FORMAT_PLANAR_YUV41X (0xe << 10) |
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#define OVERLAY_PACKED_ORDER_YUY2 (0x0 << 14) |
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#define OVERLAY_PACKED_ORDER_YVYU (0x1 << 14) |
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#define OVERLAY_PACKED_ORDER_UYVY (0x2 << 14) |
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#define OVERLAY_PACKED_ORDER_VYUY (0x3 << 14) |
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#define OVERLAY_PACKED_ORDER_MASK (0x3 << 14) |
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#define OVERLAY_MEMORY_LAYOUT_TILED (0x1 << 19) |
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#define OVERLAY_MEMORY_LAYOUT_LINEAR (0x0 << 19) |
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#define OVERLAY_MIRRORING_NORMAL (0x0 << 17) |
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#define OVERLAY_MIRRORING_HORIZONTAL (0x1 << 17) |
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#define OVERLAY_MIRRORING_VERTIACAL (0x2 << 17) |
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#define OVERLAY_MIRRORING_BOTH (0x3 << 17) |
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#define BUF_TYPE (0x1<<5) |
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#define BUF_TYPE_FRAME (0x0<<5) |
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#define BUF_TYPE_FIELD (0x1<<5) |
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#define TEST_MODE (0x1<<4) |
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#define BUFFER_SELECT (0x3<<2) |
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#define BUFFER0 (0x0<<2) |
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#define BUFFER1 (0x1<<2) |
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#define FIELD_SELECT (0x1<<1) |
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#define FIELD0 (0x0<<1) |
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#define FIELD1 (0x1<<1) |
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#define OVERLAY_ENABLE 0x1 |
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// Overlay contorl registers |
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typedef struct { |
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uint32_t OBUF_0Y; |
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uint32_t OBUF_1Y; |
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uint32_t OBUF_0U; |
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uint32_t OBUF_0V; |
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uint32_t OBUF_1U; |
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uint32_t OBUF_1V; |
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uint32_t OSTRIDE; |
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uint32_t YRGB_VPH; |
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uint32_t UV_VPH; |
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uint32_t HORZ_PH; |
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uint32_t INIT_PHS; |
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uint32_t DWINPOS; |
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uint32_t DWINSZ; |
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uint32_t SWIDTH; |
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uint32_t SWIDTHSW; |
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uint32_t SHEIGHT; |
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uint32_t YRGBSCALE; |
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uint32_t UVSCALE; |
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uint32_t OCLRC0; |
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uint32_t OCLRC1; |
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uint32_t DCLRKV; |
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uint32_t DCLRKM; |
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uint32_t SCHRKVH; |
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uint32_t SCHRKVL; |
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uint32_t SCHRKEN; |
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uint32_t OCONFIG; |
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uint32_t OCMD; |
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uint32_t RESERVED1; |
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uint32_t OSTART_0Y; |
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uint32_t OSTART_1Y; |
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uint32_t OSTART_0U; |
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uint32_t OSTART_0V; |
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uint32_t OSTART_1U; |
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uint32_t OSTART_1V; |
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uint32_t OTILEOFF_0Y; |
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uint32_t OTILEOFF_1Y; |
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uint32_t OTILEOFF_0U; |
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uint32_t OTILEOFF_0V; |
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uint32_t OTILEOFF_1U; |
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uint32_t OTILEOFF_1V; |
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uint32_t FASTHSCALE; |
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uint32_t UVSCALEV; |
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uint32_t RESERVEDC[(0x200 - 0xA8) / 4]; |
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uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; |
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uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; |
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uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; |
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uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; |
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uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; |
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uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; |
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uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; |
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uint16_t RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; |
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} OverlayBackBufferBlk; |
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typedef struct { |
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uint8_t sign; |
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uint16_t mantissa; |
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uint8_t exponent; |
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} coeffRec, *coeffPtr; |
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} // namespace intel |
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} // nam |
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#endif
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