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511 lines
13 KiB
511 lines
13 KiB
/* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 and |
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* only version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#ifndef __MSMB_ISP__ |
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#define __MSMB_ISP__ |
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#include <linux/videodev2.h> |
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#define MAX_PLANES_PER_STREAM 3 |
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#define MAX_NUM_STREAM 7 |
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#define ISP_VERSION_46 46 |
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#define ISP_VERSION_44 44 |
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#define ISP_VERSION_40 40 |
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#define ISP_VERSION_32 32 |
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#define ISP_NATIVE_BUF_BIT (0x10000 << 0) |
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#define ISP0_BIT (0x10000 << 1) |
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#define ISP1_BIT (0x10000 << 2) |
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#define ISP_META_CHANNEL_BIT (0x10000 << 3) |
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#define ISP_SCRATCH_BUF_BIT (0x10000 << 4) |
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#define ISP_STATS_STREAM_BIT 0x80000000 |
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struct msm_vfe_cfg_cmd_list; |
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enum ISP_START_PIXEL_PATTERN { |
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ISP_BAYER_RGRGRG, |
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ISP_BAYER_GRGRGR, |
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ISP_BAYER_BGBGBG, |
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ISP_BAYER_GBGBGB, |
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ISP_YUV_YCbYCr, |
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ISP_YUV_YCrYCb, |
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ISP_YUV_CbYCrY, |
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ISP_YUV_CrYCbY, |
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ISP_PIX_PATTERN_MAX |
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}; |
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enum msm_vfe_plane_fmt { |
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Y_PLANE, |
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CB_PLANE, |
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CR_PLANE, |
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CRCB_PLANE, |
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CBCR_PLANE, |
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VFE_PLANE_FMT_MAX |
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}; |
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enum msm_vfe_input_src { |
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VFE_PIX_0, |
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VFE_RAW_0, |
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VFE_RAW_1, |
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VFE_RAW_2, |
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VFE_SRC_MAX, |
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}; |
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enum msm_vfe_axi_stream_src { |
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PIX_ENCODER, |
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PIX_VIEWFINDER, |
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PIX_VIDEO, |
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CAMIF_RAW, |
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IDEAL_RAW, |
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RDI_INTF_0, |
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RDI_INTF_1, |
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RDI_INTF_2, |
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VFE_AXI_SRC_MAX |
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}; |
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enum msm_vfe_frame_skip_pattern { |
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NO_SKIP, |
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EVERY_2FRAME, |
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EVERY_3FRAME, |
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EVERY_4FRAME, |
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EVERY_5FRAME, |
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EVERY_6FRAME, |
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EVERY_7FRAME, |
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EVERY_8FRAME, |
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EVERY_16FRAME, |
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EVERY_32FRAME, |
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SKIP_ALL, |
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MAX_SKIP, |
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}; |
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enum msm_vfe_camif_input { |
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CAMIF_DISABLED, |
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CAMIF_PAD_REG_INPUT, |
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CAMIF_MIDDI_INPUT, |
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CAMIF_MIPI_INPUT, |
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}; |
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struct msm_vfe_camif_cfg { |
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uint32_t lines_per_frame; |
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uint32_t pixels_per_line; |
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uint32_t first_pixel; |
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uint32_t last_pixel; |
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uint32_t first_line; |
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uint32_t last_line; |
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uint32_t epoch_line0; |
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uint32_t epoch_line1; |
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enum msm_vfe_camif_input camif_input; |
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}; |
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enum msm_vfe_inputmux { |
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CAMIF, |
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TESTGEN, |
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EXTERNAL_READ, |
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}; |
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enum msm_vfe_stats_composite_group { |
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STATS_COMPOSITE_GRP_NONE, |
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STATS_COMPOSITE_GRP_1, |
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STATS_COMPOSITE_GRP_2, |
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STATS_COMPOSITE_GRP_MAX, |
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}; |
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struct msm_vfe_pix_cfg { |
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struct msm_vfe_camif_cfg camif_cfg; |
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enum msm_vfe_inputmux input_mux; |
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enum ISP_START_PIXEL_PATTERN pixel_pattern; |
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uint32_t input_format; |
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}; |
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struct msm_vfe_rdi_cfg { |
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uint8_t cid; |
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uint8_t frame_based; |
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}; |
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struct msm_vfe_input_cfg { |
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union { |
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struct msm_vfe_pix_cfg pix_cfg; |
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struct msm_vfe_rdi_cfg rdi_cfg; |
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} d; |
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enum msm_vfe_input_src input_src; |
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uint32_t input_pix_clk; |
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}; |
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struct msm_vfe_axi_plane_cfg { |
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uint32_t output_width; /*Include padding*/ |
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uint32_t output_height; |
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uint32_t output_stride; |
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uint32_t output_scan_lines; |
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uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ |
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uint32_t plane_addr_offset; |
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uint8_t csid_src; /*RDI 0-2*/ |
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uint8_t rdi_cid;/*CID 1-16*/ |
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}; |
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struct msm_vfe_axi_stream_request_cmd { |
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uint32_t session_id; |
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uint32_t stream_id; |
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uint32_t vt_enable; |
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uint32_t output_format;/*Planar/RAW/Misc*/ |
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enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ |
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struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; |
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uint32_t burst_count; |
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uint32_t hfr_mode; |
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uint8_t frame_base; |
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uint32_t init_frame_drop; /*MAX 31 Frames*/ |
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enum msm_vfe_frame_skip_pattern frame_skip_pattern; |
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uint8_t buf_divert; /* if TRUE no vb2 buf done. */ |
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/*Return values*/ |
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uint32_t axi_stream_handle; |
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uint32_t controllable_output; |
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}; |
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struct msm_vfe_axi_stream_release_cmd { |
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uint32_t stream_handle; |
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}; |
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enum msm_vfe_axi_stream_cmd { |
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STOP_STREAM, |
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START_STREAM, |
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STOP_IMMEDIATELY, |
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}; |
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struct msm_vfe_axi_stream_cfg_cmd { |
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uint8_t num_streams; |
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uint32_t stream_handle[MAX_NUM_STREAM]; |
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enum msm_vfe_axi_stream_cmd cmd; |
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}; |
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enum msm_vfe_axi_stream_update_type { |
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ENABLE_STREAM_BUF_DIVERT, |
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DISABLE_STREAM_BUF_DIVERT, |
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UPDATE_STREAM_FRAMEDROP_PATTERN, |
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UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, |
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UPDATE_STREAM_AXI_CONFIG, |
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UPDATE_STREAM_REQUEST_FRAMES, |
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UPDATE_STREAM_ADD_BUFQ, |
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UPDATE_STREAM_REMOVE_BUFQ, |
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}; |
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enum msm_vfe_iommu_type { |
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IOMMU_ATTACH, |
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IOMMU_DETACH, |
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}; |
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struct msm_vfe_axi_stream_cfg_update_info { |
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uint32_t stream_handle; |
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uint32_t output_format; |
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uint32_t user_stream_id; |
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uint8_t need_divert; |
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enum msm_vfe_frame_skip_pattern skip_pattern; |
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struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; |
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}; |
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struct msm_vfe_axi_stream_update_cmd { |
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uint32_t num_streams; |
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enum msm_vfe_axi_stream_update_type update_type; |
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struct msm_vfe_axi_stream_cfg_update_info update_info[MAX_NUM_STREAM]; |
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uint32_t cur_frame_id; |
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}; |
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struct msm_vfe_smmu_attach_cmd { |
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uint32_t security_mode; |
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uint32_t iommu_attach_mode; |
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}; |
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enum msm_isp_stats_type { |
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MSM_ISP_STATS_AEC, /* legacy based AEC */ |
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MSM_ISP_STATS_AF, /* legacy based AF */ |
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MSM_ISP_STATS_AWB, /* legacy based AWB */ |
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MSM_ISP_STATS_RS, /* legacy based RS */ |
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MSM_ISP_STATS_CS, /* legacy based CS */ |
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MSM_ISP_STATS_IHIST, /* legacy based HIST */ |
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MSM_ISP_STATS_SKIN, /* legacy based SKIN */ |
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MSM_ISP_STATS_BG, /* Bayer Grids */ |
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MSM_ISP_STATS_BF, /* Bayer Focus */ |
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MSM_ISP_STATS_BE, /* Bayer Exposure*/ |
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MSM_ISP_STATS_BHIST, /* Bayer Hist */ |
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MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */ |
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MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */ |
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MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */ |
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MSM_ISP_STATS_MAX /* MAX */ |
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}; |
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struct msm_vfe_stats_stream_request_cmd { |
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uint32_t session_id; |
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uint32_t stream_id; |
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enum msm_isp_stats_type stats_type; |
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uint32_t composite_flag; |
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uint32_t framedrop_pattern; |
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uint32_t init_frame_drop; /*MAX 31 Frames*/ |
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uint32_t irq_subsample_pattern; |
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uint32_t buffer_offset; |
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uint32_t stream_handle; |
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}; |
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struct msm_vfe_stats_stream_release_cmd { |
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uint32_t stream_handle; |
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}; |
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struct msm_vfe_stats_stream_cfg_cmd { |
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uint8_t num_streams; |
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uint32_t stream_handle[MSM_ISP_STATS_MAX]; |
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uint8_t enable; |
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}; |
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enum msm_vfe_reg_cfg_type { |
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VFE_WRITE, |
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VFE_WRITE_MB, |
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VFE_READ, |
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VFE_CFG_MASK, |
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VFE_WRITE_DMI_16BIT, |
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VFE_WRITE_DMI_32BIT, |
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VFE_WRITE_DMI_64BIT, |
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VFE_READ_DMI_16BIT, |
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VFE_READ_DMI_32BIT, |
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VFE_READ_DMI_64BIT, |
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GET_MAX_CLK_RATE, |
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GET_ISP_ID, |
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}; |
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struct msm_vfe_cfg_cmd2 { |
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uint16_t num_cfg; |
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uint16_t cmd_len; |
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void __user *cfg_data; |
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void __user *cfg_cmd; |
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}; |
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struct msm_vfe_cfg_cmd_list { |
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struct msm_vfe_cfg_cmd2 cfg_cmd; |
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struct msm_vfe_cfg_cmd_list *next; |
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uint32_t next_size; |
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}; |
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struct msm_vfe_reg_rw_info { |
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uint32_t reg_offset; |
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uint32_t cmd_data_offset; |
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uint32_t len; |
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}; |
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struct msm_vfe_reg_mask_info { |
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uint32_t reg_offset; |
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uint32_t mask; |
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uint32_t val; |
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}; |
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struct msm_vfe_reg_dmi_info { |
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uint32_t hi_tbl_offset; /*Optional*/ |
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uint32_t lo_tbl_offset; /*Required*/ |
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uint32_t len; |
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}; |
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struct msm_vfe_reg_cfg_cmd { |
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union { |
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struct msm_vfe_reg_rw_info rw_info; |
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struct msm_vfe_reg_mask_info mask_info; |
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struct msm_vfe_reg_dmi_info dmi_info; |
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} u; |
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enum msm_vfe_reg_cfg_type cmd_type; |
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}; |
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enum msm_isp_buf_type { |
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ISP_PRIVATE_BUF, |
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ISP_SHARE_BUF, |
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MAX_ISP_BUF_TYPE, |
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}; |
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struct msm_isp_buf_request { |
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uint32_t session_id; |
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uint32_t stream_id; |
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uint8_t num_buf; |
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uint32_t handle; |
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enum msm_isp_buf_type buf_type; |
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}; |
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struct msm_isp_qbuf_plane { |
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uint32_t addr; |
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uint32_t offset; |
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}; |
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struct msm_isp_qbuf_buffer { |
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struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; |
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uint32_t num_planes; |
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}; |
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struct msm_isp_qbuf_info { |
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uint32_t handle; |
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int32_t buf_idx; |
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/*Only used for prepare buffer*/ |
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struct msm_isp_qbuf_buffer buffer; |
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/*Only used for diverted buffer*/ |
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uint32_t dirty_buf; |
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}; |
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struct msm_vfe_axi_src_state { |
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enum msm_vfe_input_src input_src; |
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uint32_t src_active; |
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}; |
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enum msm_isp_event_idx { |
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ISP_REG_UPDATE = 0, |
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ISP_START_ACK = 1, |
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ISP_STOP_ACK = 2, |
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ISP_IRQ_VIOLATION = 3, |
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ISP_WM_BUS_OVERFLOW = 4, |
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ISP_STATS_OVERFLOW = 5, |
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ISP_CAMIF_ERROR = 6, |
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ISP_EPOCH0_IRQ = 7, |
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ISP_BUF_DONE = 9, |
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ISP_UPDATE_AXI_DONE = 10, |
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ISP_EVENT_MAX = 11 |
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}; |
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enum msm_isp_epoch_idx { |
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ISP_EPOCH_0 = 0, |
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ISP_EPOCH_1 = 1, |
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ISP_EPOCH_MAX = 2 |
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}; |
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#define ISP_EVENT_OFFSET 8 |
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#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) |
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#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) |
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#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) |
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#define ISP_SOF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) |
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#define ISP_EOF_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) |
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#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) |
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#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) |
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#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) |
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#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) |
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#define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW) |
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#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) |
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#define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR) |
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#define ISP_EVENT_EPOCH0_IRQ (ISP_EVENT_BASE + ISP_EPOCH0_IRQ) |
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#define ISP_EVENT_UPDATE_AXI_DONE (ISP_EVENT_BASE + ISP_UPDATE_AXI_DONE) |
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#define ISP_EVENT_SOF (ISP_SOF_EVENT_BASE) |
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#define ISP_EVENT_EOF (ISP_EOF_EVENT_BASE) |
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#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) |
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#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) |
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#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) |
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#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) |
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/* The msm_v4l2_event_data structure should match the |
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* v4l2_event.u.data field. |
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* should not exceed 64 bytes */ |
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struct msm_isp_buf_event { |
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uint32_t session_id; |
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uint32_t stream_id; |
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uint32_t handle; |
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uint32_t output_format; |
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int8_t buf_idx; |
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}; |
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struct msm_isp_stats_event { |
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uint32_t stats_mask; /* 4 bytes */ |
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uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ |
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}; |
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struct msm_isp_stream_ack { |
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uint32_t session_id; |
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uint32_t stream_id; |
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uint32_t handle; |
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}; |
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struct msm_isp_epoch_event { |
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enum msm_isp_epoch_idx epoch_idx; |
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}; |
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struct msm_isp_event_data { |
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/*Wall clock except for buffer divert events |
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*which use monotonic clock |
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*/ |
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struct timeval timestamp; |
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/* Monotonic timestamp since bootup */ |
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struct timeval mono_timestamp; |
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enum msm_vfe_input_src input_intf; |
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uint32_t frame_id; |
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union { |
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struct msm_isp_stats_event stats; |
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struct msm_isp_buf_event buf_done; |
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struct msm_isp_epoch_event epoch; |
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} u; /* union can have max 52 bytes */ |
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}; |
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#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') |
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#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') |
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#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') |
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#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') |
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#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') |
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#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') |
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#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') |
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#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') |
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#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') |
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#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') |
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#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') |
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#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') |
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#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') |
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#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') |
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#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') |
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#define VIDIOC_MSM_VFE_REG_CFG \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) |
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#define VIDIOC_MSM_ISP_REQUEST_BUF \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request) |
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#define VIDIOC_MSM_ISP_ENQUEUE_BUF \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info) |
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#define VIDIOC_MSM_ISP_RELEASE_BUF \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request) |
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#define VIDIOC_MSM_ISP_REQUEST_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd) |
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#define VIDIOC_MSM_ISP_CFG_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd) |
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#define VIDIOC_MSM_ISP_RELEASE_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd) |
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#define VIDIOC_MSM_ISP_INPUT_CFG \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg) |
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#define VIDIOC_MSM_ISP_SET_SRC_STATE \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state) |
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#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+9, \ |
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struct msm_vfe_stats_stream_request_cmd) |
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#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd) |
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#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+11, \ |
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struct msm_vfe_stats_stream_release_cmd) |
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#define VIDIOC_MSM_ISP_UPDATE_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd) |
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#define VIDIOC_MSM_VFE_REG_LIST_CFG \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list) |
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#define VIDIOC_MSM_ISP_SMMU_ATTACH \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd) |
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#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd) |
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#define VIDIOC_MSM_ISP_DEQUEUE_BUF \ |
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_IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_isp_qbuf_info) |
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#endif /* __MSMB_ISP__ */
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