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232 lines
6.7 KiB
232 lines
6.7 KiB
/* |
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* Copyright 2010 Tilera Corporation. All Rights Reserved. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation, version 2. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
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* NON INFRINGEMENT. See the GNU General Public License for |
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* more details. |
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*/ |
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#ifndef _ASM_TILE_PCI_H |
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#define _ASM_TILE_PCI_H |
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#include <linux/dma-mapping.h> |
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#include <linux/pci.h> |
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#include <asm-generic/pci_iomap.h> |
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#ifndef __tilegx__ |
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/* |
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* Structure of a PCI controller (host bridge) |
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*/ |
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struct pci_controller { |
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int index; /* PCI domain number */ |
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struct pci_bus *root_bus; |
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int last_busno; |
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int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */ |
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int hv_mem_fd; /* fd to Hypervisor for MMIO operations */ |
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struct pci_ops *ops; |
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int irq_base; /* Base IRQ from the Hypervisor */ |
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int plx_gen1; /* flag for PLX Gen 1 configuration */ |
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/* Address ranges that are routed to this controller/bridge. */ |
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struct resource mem_resources[3]; |
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}; |
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/* |
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* This flag tells if the platform is TILEmpower that needs |
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* special configuration for the PLX switch chip. |
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*/ |
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extern int tile_plx_gen1; |
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} |
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#define TILE_NUM_PCIE 2 |
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/* |
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* The hypervisor maps the entirety of CPA-space as bus addresses, so |
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* bus addresses are physical addresses. The networking and block |
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* device layers use this boolean for bounce buffer decisions. |
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*/ |
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#define PCI_DMA_BUS_IS_PHYS 1 |
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/* generic pci stuff */ |
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#include <asm-generic/pci.h> |
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#else |
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#include <asm/page.h> |
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#include <gxio/trio.h> |
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/** |
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* We reserve the hugepage-size address range at the top of the 64-bit address |
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* space to serve as the PCI window, emulating the BAR0 space of an endpoint |
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* device. This window is used by the chip-to-chip applications running on |
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* the RC node. The reason for carving out this window is that Mem-Maps that |
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* back up this window will not overlap with those that map the real physical |
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* memory. |
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*/ |
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#define PCIE_HOST_BAR0_SIZE HPAGE_SIZE |
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#define PCIE_HOST_BAR0_START HPAGE_MASK |
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/** |
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* The first PAGE_SIZE of the above "BAR" window is mapped to the |
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* gxpci_host_regs structure. |
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*/ |
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#define PCIE_HOST_REGS_SIZE PAGE_SIZE |
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/* |
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* This is the PCI address where the Mem-Map interrupt regions start. |
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* We use the 2nd to the last huge page of the 64-bit address space. |
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* The last huge page is used for the rootcomplex "bar", for C2C purpose. |
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*/ |
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#define MEM_MAP_INTR_REGIONS_BASE (HPAGE_MASK - HPAGE_SIZE) |
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/* |
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* Each Mem-Map interrupt region occupies 4KB. |
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*/ |
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#define MEM_MAP_INTR_REGION_SIZE (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT) |
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/* |
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* Allocate the PCI BAR window right below 4GB. |
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*/ |
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#define TILE_PCI_BAR_WINDOW_TOP (1ULL << 32) |
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/* |
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* Allocate 1GB for the PCI BAR window. |
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*/ |
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#define TILE_PCI_BAR_WINDOW_SIZE (1 << 30) |
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/* |
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* This is the highest bus address targeting the host memory that |
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* can be generated by legacy PCI devices with 32-bit or less |
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* DMA capability, dictated by the BAR window size and location. |
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*/ |
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#define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \ |
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(TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1) |
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/* |
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* We shift the PCI bus range for all the physical memory up by the whole PA |
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* range. The corresponding CPA of an incoming PCI request will be the PCI |
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* address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies |
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* that the 64-bit capable devices will be given DMA addresses as |
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* the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit |
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* devices, we create a separate map region that handles the low |
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* 4GB. |
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* |
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* This design lets us avoid the "PCI hole" problem where the host bridge |
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* won't pass DMA traffic with target addresses that happen to fall within the |
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* BAR space. This enables us to use all the physical memory for DMA, instead |
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* of wasting the same amount of physical memory as the BAR window size. |
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*/ |
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#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH()) |
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/* |
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* Start of the PCI memory resource, which starts at the end of the |
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* maximum system physical RAM address. |
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*/ |
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#define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH()) |
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/* |
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* Structure of a PCI controller (host bridge) on Gx. |
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*/ |
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struct pci_controller { |
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/* Pointer back to the TRIO that this PCIe port is connected to. */ |
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gxio_trio_context_t *trio; |
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int mac; /* PCIe mac index on the TRIO shim */ |
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int trio_index; /* Index of TRIO shim that contains the MAC. */ |
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int pio_mem_index; /* PIO region index for memory access */ |
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#ifdef CONFIG_TILE_PCI_IO |
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int pio_io_index; /* PIO region index for I/O space access */ |
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#endif |
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/* |
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* Mem-Map regions for all the memory controllers so that Linux can |
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* map all of its physical memory space to the PCI bus. |
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*/ |
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int mem_maps[MAX_NUMNODES]; |
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int index; /* PCI domain number */ |
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struct pci_bus *root_bus; |
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/* PCI I/O space resource for this controller. */ |
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struct resource io_space; |
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char io_space_name[32]; |
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/* PCI memory space resource for this controller. */ |
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struct resource mem_space; |
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char mem_space_name[32]; |
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uint64_t mem_offset; /* cpu->bus memory mapping offset. */ |
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int first_busno; |
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struct pci_ops *ops; |
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/* Table that maps the INTx numbers to Linux irq numbers. */ |
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int irq_intx_table[4]; |
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}; |
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extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES]; |
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extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; |
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extern int num_trio_shims; |
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *); |
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/* |
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* The PCI address space does not equal the physical memory address |
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* space (we have an IOMMU). The IDE and SCSI device layers use this |
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* boolean for bounce buffer decisions. |
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*/ |
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#define PCI_DMA_BUS_IS_PHYS 0 |
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#endif /* __tilegx__ */ |
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int __init tile_pci_init(void); |
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int __init pcibios_init(void); |
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void pcibios_fixup_bus(struct pci_bus *bus); |
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#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index) |
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/* |
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* This decides whether to display the domain number in /proc. |
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*/ |
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static inline int pci_proc_domain(struct pci_bus *bus) |
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{ |
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return 1; |
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} |
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/* |
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* pcibios_assign_all_busses() tells whether or not the bus numbers |
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* should be reassigned, in case the BIOS didn't do it correctly, or |
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* in case we don't have a BIOS and we want to let Linux do it. |
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*/ |
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static inline int pcibios_assign_all_busses(void) |
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{ |
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return 1; |
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} |
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#define PCIBIOS_MIN_MEM 0 |
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/* Minimum PCI I/O address, starting at the page boundary. */ |
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#define PCIBIOS_MIN_IO PAGE_SIZE |
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/* Use any cpu for PCI. */ |
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#define cpumask_of_pcibus(bus) cpu_online_mask |
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/* implement the pci_ DMA API in terms of the generic device dma_ one */ |
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#include <asm-generic/pci-dma-compat.h> |
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#endif /* _ASM_TILE_PCI_H */
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