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349 lines
12 KiB
349 lines
12 KiB
/* libs/pixelflinger/codeflinger/ARMAssemblerInterface.h |
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** |
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** Copyright 2006, The Android Open Source Project |
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** |
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** Licensed under the Apache License, Version 2.0 (the "License"); |
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** you may not use this file except in compliance with the License. |
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** You may obtain a copy of the License at |
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** |
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** http://www.apache.org/licenses/LICENSE-2.0 |
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** |
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** Unless required by applicable law or agreed to in writing, software |
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** distributed under the License is distributed on an "AS IS" BASIS, |
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** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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** See the License for the specific language governing permissions and |
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** limitations under the License. |
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*/ |
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#ifndef ANDROID_ARMASSEMBLER_INTERFACE_H |
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#define ANDROID_ARMASSEMBLER_INTERFACE_H |
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#include <stdint.h> |
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#include <sys/types.h> |
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namespace android { |
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// ---------------------------------------------------------------------------- |
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class ARMAssemblerInterface |
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{ |
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public: |
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virtual ~ARMAssemblerInterface(); |
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enum { |
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EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV, |
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HS = CS, |
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LO = CC |
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}; |
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enum { |
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S = 1 |
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}; |
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enum { |
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LSL, LSR, ASR, ROR |
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}; |
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enum { |
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ED, FD, EA, FA, |
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IB, IA, DB, DA |
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}; |
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enum { |
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R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, |
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SP = R13, |
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LR = R14, |
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PC = R15 |
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}; |
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enum { |
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#define LIST(rr) L##rr=1<<rr |
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LIST(R0), LIST(R1), LIST(R2), LIST(R3), LIST(R4), LIST(R5), LIST(R6), |
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LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12), |
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LIST(R13), LIST(R14), LIST(R15), |
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LIST(SP), LIST(LR), LIST(PC), |
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#undef LIST |
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LSAVED = LR4|LR5|LR6|LR7|LR8|LR9|LR10|LR11 | LLR |
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}; |
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enum { |
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CODEGEN_ARCH_ARM = 1, CODEGEN_ARCH_MIPS, CODEGEN_ARCH_ARM64, CODEGEN_ARCH_MIPS64 |
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}; |
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// ----------------------------------------------------------------------- |
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// shifters and addressing modes |
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// ----------------------------------------------------------------------- |
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// these static versions are used for initializers on LDxx/STxx below |
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static uint32_t __immed12_pre(int32_t immed12, int W=0); |
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static uint32_t __immed8_pre(int32_t immed12, int W=0); |
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virtual bool isValidImmediate(uint32_t immed) = 0; |
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virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm) = 0; |
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virtual uint32_t imm(uint32_t immediate) = 0; |
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virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0; |
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virtual uint32_t reg_rrx(int Rm) = 0; |
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virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0; |
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// addressing modes... |
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// LDR(B)/STR(B)/PLD |
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// (immediate and Rm can be negative, which indicates U=0) |
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virtual uint32_t immed12_pre(int32_t immed12, int W=0) = 0; |
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virtual uint32_t immed12_post(int32_t immed12) = 0; |
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virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0; |
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virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0; |
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// LDRH/LDRSB/LDRSH/STRH |
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// (immediate and Rm can be negative, which indicates U=0) |
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virtual uint32_t immed8_pre(int32_t immed8, int W=0) = 0; |
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virtual uint32_t immed8_post(int32_t immed8) = 0; |
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virtual uint32_t reg_pre(int Rm, int W=0) = 0; |
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virtual uint32_t reg_post(int Rm) = 0; |
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// ----------------------------------------------------------------------- |
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// basic instructions & code generation |
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// ----------------------------------------------------------------------- |
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// generate the code |
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virtual void reset() = 0; |
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virtual int generate(const char* name) = 0; |
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virtual void disassemble(const char* name) = 0; |
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virtual int getCodegenArch() = 0; |
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// construct prolog and epilog |
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virtual void prolog() = 0; |
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virtual void epilog(uint32_t touched) = 0; |
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virtual void comment(const char* string) = 0; |
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// data processing... |
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enum { |
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opAND, opEOR, opSUB, opRSB, opADD, opADC, opSBC, opRSC, |
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opTST, opTEQ, opCMP, opCMN, opORR, opMOV, opBIC, opMVN, |
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opADD64, opSUB64 |
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}; |
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virtual void |
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dataProcessing( int opcode, int cc, int s, |
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int Rd, int Rn, |
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uint32_t Op2) = 0; |
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// multiply... |
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virtual void MLA(int cc, int s, |
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int Rd, int Rm, int Rs, int Rn) = 0; |
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virtual void MUL(int cc, int s, |
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int Rd, int Rm, int Rs) = 0; |
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virtual void UMULL(int cc, int s, |
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int RdLo, int RdHi, int Rm, int Rs) = 0; |
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virtual void UMUAL(int cc, int s, |
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int RdLo, int RdHi, int Rm, int Rs) = 0; |
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virtual void SMULL(int cc, int s, |
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int RdLo, int RdHi, int Rm, int Rs) = 0; |
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virtual void SMUAL(int cc, int s, |
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int RdLo, int RdHi, int Rm, int Rs) = 0; |
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// branches... |
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virtual void B(int cc, uint32_t* pc) = 0; |
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virtual void BL(int cc, uint32_t* pc) = 0; |
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virtual void BX(int cc, int Rn) = 0; |
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virtual void label(const char* theLabel) = 0; |
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virtual void B(int cc, const char* label) = 0; |
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virtual void BL(int cc, const char* label) = 0; |
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// valid only after generate() has been called |
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virtual uint32_t* pcForLabel(const char* label) = 0; |
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// data transfer... |
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virtual void LDR (int cc, int Rd, |
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int Rn, uint32_t offset = __immed12_pre(0)) = 0; |
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virtual void LDRB(int cc, int Rd, |
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int Rn, uint32_t offset = __immed12_pre(0)) = 0; |
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virtual void STR (int cc, int Rd, |
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int Rn, uint32_t offset = __immed12_pre(0)) = 0; |
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virtual void STRB(int cc, int Rd, |
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int Rn, uint32_t offset = __immed12_pre(0)) = 0; |
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virtual void LDRH (int cc, int Rd, |
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int Rn, uint32_t offset = __immed8_pre(0)) = 0; |
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virtual void LDRSB(int cc, int Rd, |
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int Rn, uint32_t offset = __immed8_pre(0)) = 0; |
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virtual void LDRSH(int cc, int Rd, |
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int Rn, uint32_t offset = __immed8_pre(0)) = 0; |
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virtual void STRH (int cc, int Rd, |
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int Rn, uint32_t offset = __immed8_pre(0)) = 0; |
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// block data transfer... |
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virtual void LDM(int cc, int dir, |
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int Rn, int W, uint32_t reg_list) = 0; |
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virtual void STM(int cc, int dir, |
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int Rn, int W, uint32_t reg_list) = 0; |
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// special... |
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virtual void SWP(int cc, int Rn, int Rd, int Rm) = 0; |
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virtual void SWPB(int cc, int Rn, int Rd, int Rm) = 0; |
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virtual void SWI(int cc, uint32_t comment) = 0; |
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// DSP instructions... |
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enum { |
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// B=0, T=1 |
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// yx |
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xyBB = 0, // 0000, |
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xyTB = 2, // 0010, |
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xyBT = 4, // 0100, |
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xyTT = 6, // 0110, |
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yB = 0, // 0000, |
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yT = 4, // 0100 |
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}; |
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virtual void PLD(int Rn, uint32_t offset) = 0; |
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virtual void CLZ(int cc, int Rd, int Rm) = 0; |
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virtual void QADD(int cc, int Rd, int Rm, int Rn) = 0; |
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virtual void QDADD(int cc, int Rd, int Rm, int Rn) = 0; |
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virtual void QSUB(int cc, int Rd, int Rm, int Rn) = 0; |
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virtual void QDSUB(int cc, int Rd, int Rm, int Rn) = 0; |
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virtual void SMUL(int cc, int xy, |
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int Rd, int Rm, int Rs) = 0; |
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virtual void SMULW(int cc, int y, |
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int Rd, int Rm, int Rs) = 0; |
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virtual void SMLA(int cc, int xy, |
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int Rd, int Rm, int Rs, int Rn) = 0; |
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virtual void SMLAL(int cc, int xy, |
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int RdHi, int RdLo, int Rs, int Rm) = 0; |
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virtual void SMLAW(int cc, int y, |
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int Rd, int Rm, int Rs, int Rn) = 0; |
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// byte/half word extract... |
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virtual void UXTB16(int cc, int Rd, int Rm, int rotate) = 0; |
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// bit manipulation... |
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virtual void UBFX(int cc, int Rd, int Rn, int lsb, int width) = 0; |
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// ----------------------------------------------------------------------- |
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// convenience... |
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// ----------------------------------------------------------------------- |
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inline void |
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ADC(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opADC, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opADD, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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AND(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opAND, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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BIC(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opBIC, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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EOR(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opEOR, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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MOV(int cc, int s, int Rd, uint32_t Op2) { |
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dataProcessing(opMOV, cc, s, Rd, 0, Op2); |
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} |
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inline void |
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MVN(int cc, int s, int Rd, uint32_t Op2) { |
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dataProcessing(opMVN, cc, s, Rd, 0, Op2); |
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} |
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inline void |
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ORR(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opORR, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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RSB(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opRSB, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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RSC(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opRSC, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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SBC(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opSBC, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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SUB(int cc, int s, int Rd, int Rn, uint32_t Op2) { |
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dataProcessing(opSUB, cc, s, Rd, Rn, Op2); |
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} |
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inline void |
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TEQ(int cc, int Rn, uint32_t Op2) { |
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dataProcessing(opTEQ, cc, 1, 0, Rn, Op2); |
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} |
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inline void |
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TST(int cc, int Rn, uint32_t Op2) { |
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dataProcessing(opTST, cc, 1, 0, Rn, Op2); |
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} |
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inline void |
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CMP(int cc, int Rn, uint32_t Op2) { |
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dataProcessing(opCMP, cc, 1, 0, Rn, Op2); |
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} |
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inline void |
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CMN(int cc, int Rn, uint32_t Op2) { |
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dataProcessing(opCMN, cc, 1, 0, Rn, Op2); |
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} |
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inline void SMULBB(int cc, int Rd, int Rm, int Rs) { |
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SMUL(cc, xyBB, Rd, Rm, Rs); } |
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inline void SMULTB(int cc, int Rd, int Rm, int Rs) { |
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SMUL(cc, xyTB, Rd, Rm, Rs); } |
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inline void SMULBT(int cc, int Rd, int Rm, int Rs) { |
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SMUL(cc, xyBT, Rd, Rm, Rs); } |
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inline void SMULTT(int cc, int Rd, int Rm, int Rs) { |
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SMUL(cc, xyTT, Rd, Rm, Rs); } |
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inline void SMULWB(int cc, int Rd, int Rm, int Rs) { |
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SMULW(cc, yB, Rd, Rm, Rs); } |
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inline void SMULWT(int cc, int Rd, int Rm, int Rs) { |
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SMULW(cc, yT, Rd, Rm, Rs); } |
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inline void |
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SMLABB(int cc, int Rd, int Rm, int Rs, int Rn) { |
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SMLA(cc, xyBB, Rd, Rm, Rs, Rn); } |
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inline void |
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SMLATB(int cc, int Rd, int Rm, int Rs, int Rn) { |
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SMLA(cc, xyTB, Rd, Rm, Rs, Rn); } |
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inline void |
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SMLABT(int cc, int Rd, int Rm, int Rs, int Rn) { |
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SMLA(cc, xyBT, Rd, Rm, Rs, Rn); } |
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inline void |
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SMLATT(int cc, int Rd, int Rm, int Rs, int Rn) { |
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SMLA(cc, xyTT, Rd, Rm, Rs, Rn); } |
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inline void |
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SMLALBB(int cc, int RdHi, int RdLo, int Rs, int Rm) { |
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SMLAL(cc, xyBB, RdHi, RdLo, Rs, Rm); } |
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inline void |
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SMLALTB(int cc, int RdHi, int RdLo, int Rs, int Rm) { |
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SMLAL(cc, xyTB, RdHi, RdLo, Rs, Rm); } |
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inline void |
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SMLALBT(int cc, int RdHi, int RdLo, int Rs, int Rm) { |
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SMLAL(cc, xyBT, RdHi, RdLo, Rs, Rm); } |
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inline void |
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SMLALTT(int cc, int RdHi, int RdLo, int Rs, int Rm) { |
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SMLAL(cc, xyTT, RdHi, RdLo, Rs, Rm); } |
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inline void |
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SMLAWB(int cc, int Rd, int Rm, int Rs, int Rn) { |
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SMLAW(cc, yB, Rd, Rm, Rs, Rn); } |
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inline void |
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SMLAWT(int cc, int Rd, int Rm, int Rs, int Rn) { |
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SMLAW(cc, yT, Rd, Rm, Rs, Rn); } |
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// Address loading/storing/manipulation |
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virtual void ADDR_LDR(int cc, int Rd, |
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int Rn, uint32_t offset = __immed12_pre(0)); |
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virtual void ADDR_STR (int cc, int Rd, |
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int Rn, uint32_t offset = __immed12_pre(0)); |
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virtual void ADDR_ADD(int cc, int s, int Rd, |
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int Rn, uint32_t Op2); |
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virtual void ADDR_SUB(int cc, int s, int Rd, |
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int Rn, uint32_t Op2); |
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}; |
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}; // namespace android |
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#endif //ANDROID_ARMASSEMBLER_INTERFACE_H
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